firrtl
package firrtl
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class
AddDescriptionNodes extends Transform
Wraps modules or statements with their respective described nodes.
Wraps modules or statements with their respective described nodes. Descriptions come from DescriptionAnnotation. Describing a module or any of its ports will turn it into a
DescribedMod
. Describing a Statement will turn it into a (private)DescribedStmt
.- Note
should only be used by VerilogEmitter, described nodes will break other transforms.
-
class
AnnotationSeq extends AnyRef
Container of all annotations for a Firrtl compiler
- case class CDefMPort(info: Info, name: String, tpe: Type, mem: String, exps: Seq[Expression], direction: MPortDir) extends Statement with HasInfo with Product with Serializable
- case class CDefMemory(info: Info, name: String, tpe: Type, size: BigInt, seq: Boolean, readUnderWrite: ir.ReadUnderWrite.Value = ReadUnderWrite.Undefined) extends Statement with HasInfo with Product with Serializable
- class ChirrtlEmitter extends FirrtlEmitter
-
class
ChirrtlToHighFirrtl extends CoreTransform
This transforms "CHIRRTL", the chisel3 IR, to "Firrtl".
This transforms "CHIRRTL", the chisel3 IR, to "Firrtl". Note the resulting circuit has only IR nodes, not WIR.
-
sealed abstract
class
CircuitForm extends Ordered[CircuitForm]
Current form of the Firrtl Circuit
Current form of the Firrtl Circuit
Form is a measure of addition restrictions on the legality of a Firrtl circuit. There is a notion of "highness" and "lowness" implemented in the compiler by extending scala.math.Ordered. "Lower" forms add additional restrictions compared to "higher" forms. This means that "higher" forms are strictly supersets of the "lower" forms. Thus, that any transform that operates on HighForm can also operate on MidForm or LowForm
-
case class
CircuitState(circuit: Circuit, form: CircuitForm, annotations: AnnotationSeq, renames: Option[RenameMap]) extends Product with Serializable
Current State of the Circuit
Current State of the Circuit
- circuit
The current state of the Firrtl AST
- form
The current form of the circuit
- annotations
The current collection of Annotation
- renames
A map of Named things that have been renamed. Generally only a return value from Transforms
- trait Compiler extends LazyLogging
- trait Constraint extends AnyRef
- sealed abstract class CoreTransform extends SeqTransform
-
case class
CustomTransformException(cause: Throwable) extends Exception with Product with Serializable
Wraps exceptions from CustomTransforms so they can be reported appropriately
- case class DescriptionAnnotation(named: Named, description: String) extends Annotation with Product with Serializable
- case class EmitAllModulesAnnotation(emitter: Class[_ <: Emitter]) extends EmitAnnotation with Product with Serializable
- sealed trait EmitAnnotation extends NoTargetAnnotation
- case class EmitCircuitAnnotation(emitter: Class[_ <: Emitter]) extends EmitAnnotation with Product with Serializable
-
sealed
trait
EmittedAnnotation[T <: EmittedComponent] extends NoTargetAnnotation
Traits for Annotations containing emitted components
- sealed abstract class EmittedCircuit extends EmittedComponent
- sealed trait EmittedCircuitAnnotation[T <: EmittedCircuit] extends EmittedAnnotation[T]
- sealed abstract class EmittedComponent extends AnyRef
- final case class EmittedFirrtlCircuit(name: String, value: String, outputSuffix: String) extends EmittedCircuit with Product with Serializable
- case class EmittedFirrtlCircuitAnnotation(value: EmittedFirrtlCircuit) extends EmittedCircuitAnnotation[EmittedFirrtlCircuit] with Product with Serializable
- final case class EmittedFirrtlModule(name: String, value: String, outputSuffix: String) extends EmittedModule with Product with Serializable
- case class EmittedFirrtlModuleAnnotation(value: EmittedFirrtlModule) extends EmittedModuleAnnotation[EmittedFirrtlModule] with Product with Serializable
- sealed abstract class EmittedModule extends EmittedComponent
- sealed trait EmittedModuleAnnotation[T <: EmittedModule] extends EmittedAnnotation[T]
- final case class EmittedVerilogCircuit(name: String, value: String, outputSuffix: String) extends EmittedCircuit with Product with Serializable
- case class EmittedVerilogCircuitAnnotation(value: EmittedVerilogCircuit) extends EmittedCircuitAnnotation[EmittedVerilogCircuit] with Product with Serializable
- final case class EmittedVerilogModule(name: String, value: String, outputSuffix: String) extends EmittedModule with Product with Serializable
- case class EmittedVerilogModuleAnnotation(value: EmittedVerilogModule) extends EmittedModuleAnnotation[EmittedVerilogModule] with Product with Serializable
-
trait
Emitter extends Transform
Defines old API for Emission.
Defines old API for Emission. Deprecated
- case class EmitterException(message: String) extends PassException with Product with Serializable
- case class ExpWidth(arg1: Width) extends Width with HasMapWidth with Product with Serializable
- sealed abstract class FirrtlEmitter extends Transform with Emitter
- final class FirrtlProtos extends AnyRef
-
class
FirrtlUserException extends RuntimeException with NoStackTrace
Exception indicating user error
Exception indicating user error
These exceptions indicate a problem due to bad input and thus do not include a stack trace. This can be extended by custom transform writers.
- trait Flow extends AnyRef
-
class
HighFirrtlCompiler extends Compiler
Emits input circuit Will replace Chirrtl constructs with Firrtl
- class HighFirrtlEmitter extends FirrtlEmitter
-
class
HighFirrtlToMiddleFirrtl extends CoreTransform
Expands aggregate connects, removes dynamic accesses, and when statements.
Expands aggregate connects, removes dynamic accesses, and when statements. Checks for uninitialized values. Must accept a well-formed graph. Operates on working IR nodes.
-
class
IRToWorkingIR extends CoreTransform
Converts from the bare intermediate representation (ir.scala) to a working representation (WIR.scala)
- case class InvalidEscapeCharException(message: String) extends ParserException with Product with Serializable
- case class InvalidStringLitException(message: String) extends ParserException with Product with Serializable
- trait Kind extends AnyRef
- abstract class LexerHelper extends AnyRef
-
class
LowFirrtlCompiler extends Compiler
Emits lowered input circuit
- class LowFirrtlEmitter extends FirrtlEmitter
-
class
LowFirrtlOptimization extends CoreTransform
Runs a series of optimization passes on LowFirrtl
Runs a series of optimization passes on LowFirrtl
- Note
This is currently required for correct Verilog emission TODO Fix the above note
- abstract class MPortDir extends FirrtlNode
- case class MaxWidth(args: Seq[Width]) extends Width with HasMapWidth with Product with Serializable
- class MemoizedHash[T] extends AnyRef
-
class
MiddleFirrtlCompiler extends Compiler
Emits middle Firrtl input circuit
- class MiddleFirrtlEmitter extends FirrtlEmitter
-
class
MiddleFirrtlToLowFirrtl extends CoreTransform
Expands all aggregate types into many ground-typed components.
Expands all aggregate types into many ground-typed components. Must accept a well-formed graph of only middle Firrtl features. Operates on working IR nodes.
- case class MinWidth(args: Seq[Width]) extends Width with HasMapWidth with Product with Serializable
-
class
MinimumLowFirrtlOptimization extends CoreTransform
Runs runs only the optimization passes needed for Verilog emission
-
class
MinimumVerilogCompiler extends Compiler
Emits Verilog without optimizations
- class MinimumVerilogEmitter extends VerilogEmitter with Emitter
- case class MinusWidth(arg1: Width, arg2: Width) extends Width with HasMapWidth with Product with Serializable
-
class
ModuleGraph extends AnyRef
Maintains a one to many graph of each modules instantiated child module.
Maintains a one to many graph of each modules instantiated child module. This graph can be searched for a path from a child module back to one of it's parents. If one is found a recursive loop has happened The graph is a map between the name of a node to set of names of that nodes children
- class Namespace extends AnyRef
-
class
NoneCompiler extends Compiler
Emits input circuit with no changes
Emits input circuit with no changes
Primarily useful for changing between .fir and .pb serialized formats
- final case class OneFilePerModule(targetDir: String) extends OutputConfig with Product with Serializable
-
sealed abstract
class
OutputConfig extends AnyRef
Firrtl output configuration specified by FirrtlExecutionOptions
Firrtl output configuration specified by FirrtlExecutionOptions
Derived from the fields of the execution options
- case class ParameterNotSpecifiedException(message: String) extends ParserException with Product with Serializable
- case class ParameterRedefinedException(message: String) extends ParserException with Product with Serializable
- class ParserException extends FirrtlUserException
- case class PlusWidth(arg1: Width, arg2: Width) extends Width with HasMapWidth with Product with Serializable
-
final
class
RenameMap extends AnyRef
Map old names to new names
Map old names to new names
Transforms that modify names should return a RenameMap with the CircuitState These are mutable datastructures for convenience
-
class
ResolveAndCheck extends CoreTransform
Resolves types, kinds, and flows, and checks the circuit legality.
Resolves types, kinds, and flows, and checks the circuit legality. Operates on working IR nodes and high Firrtl.
-
trait
ResolvedAnnotationPaths extends AnyRef
Extend for transforms that require resolved targets in their annotations Ensures all targets in annotations of a class in annotationClasses are resolved before the execute method
-
abstract
class
SeqTransform extends Transform with SeqTransformBased
For transformations that are simply a sequence of transforms
- trait SeqTransformBased extends AnyRef
- final case class SingleFile(targetFile: String) extends OutputConfig with Product with Serializable
- case class SyntaxErrorsException(message: String) extends ParserException with Product with Serializable
-
class
SystemVerilogCompiler extends VerilogCompiler
Currently just an alias for the VerilogCompiler
- class SystemVerilogEmitter extends VerilogEmitter
-
abstract
class
Transform extends TransformLike[CircuitState]
The basic unit of operating on a Firrtl AST
- case class VRandom(width: BigInt) extends Expression with Product with Serializable
- case class VarWidth(name: String) extends Width with HasMapWidth with Product with Serializable
-
class
VerilogCompiler extends Compiler
Emits Verilog
- class VerilogEmitter extends SeqTransform with Emitter
- class Visitor extends AbstractParseTreeVisitor[FirrtlNode] with ParseTreeVisitor[FirrtlNode]
- case class WDefInstance(info: Info, name: String, module: String, tpe: Type) extends Statement with IsDeclaration with Product with Serializable
- case class WDefInstanceConnector(info: Info, name: String, module: String, tpe: Type, portCons: Seq[(Expression, Expression)]) extends Statement with IsDeclaration with Product with Serializable
- class WGeq extends Constraint
- case class WRef(name: String, tpe: Type, kind: Kind, flow: Flow) extends Expression with GenderFromFlow with Product with Serializable
- case class WSubAccess(expr: Expression, index: Expression, tpe: Type, flow: Flow) extends Expression with GenderFromFlow with Product with Serializable
- case class WSubField(expr: Expression, name: String, tpe: Type, flow: Flow) extends Expression with GenderFromFlow with Product with Serializable
- case class WSubIndex(expr: Expression, value: Int, tpe: Type, flow: Flow) extends Expression with GenderFromFlow with Product with Serializable
- class WrappedExpression extends AnyRef
- class WrappedType extends AnyRef
- class WrappedWidth extends AnyRef
-
case class
CommonOptions(topName: String = "", targetDirName: String = ".", globalLogLevel: logger.LogLevel.Value = LogLevel.None, logToFile: Boolean = false, logClassNames: Boolean = false, classLogLevels: Map[String, logger.LogLevel.Value] = Map.empty, programArgs: Seq[String] = Seq.empty) extends ComposableOptions with Product with Serializable
Most of the chisel toolchain components require a topName which defines a circuit or a device under test.
Most of the chisel toolchain components require a topName which defines a circuit or a device under test. Much of the work that is done takes place in a directory. It would be simplest to require topName to be defined but in practice it is preferred to defer this. For example, in chisel, by deferring this it is possible for the execute there to first elaborate the circuit and then set the topName from that if it has not already been set.
- Annotations
- @deprecated
- Deprecated
(Since version 1.2) Use a FirrtlOptionsView, LoggerOptionsView, or construct your own view of an AnnotationSeq
-
trait
ComposableOptions extends AnyRef
Use this trait to define an options class that can add its private command line options to a externally declared parser.
Use this trait to define an options class that can add its private command line options to a externally declared parser. NOTE In all derived trait/classes, if you intend on maintaining backwards compatibility, be sure to add new options at the end of the current ones and don't remove any existing ones.
- Annotations
- @deprecated
- Deprecated
(Since version 1.2) Use firrtl.options.HasScoptOptions and/or library/transform registration
-
class
ExecutionOptionsManager extends HasParser with HasCommonOptions
- Annotations
- @deprecated
- Deprecated
(Since version 1.2) Use new FirrtlStage infrastructure
-
class
FIRRTLException extends RuntimeException
- Annotations
- @deprecated
- Deprecated
(Since version 1.2) External users should use either FirrtlUserException or their own hierarchy
-
case class
FirrtlExecutionFailure(message: String) extends FirrtlExecutionResult with Product with Serializable
The firrtl compilation failed.
The firrtl compilation failed.
- message
Some kind of hint as to what went wrong.
- Annotations
- @deprecated
- Deprecated
(Since version 1.2) Use FirrtlStage and examine the output AnnotationSeq directly
-
case class
FirrtlExecutionOptions(inputFileNameOverride: String = "", outputFileNameOverride: String = "", compilerName: String = "verilog", infoModeName: String = "append", inferRW: Seq[String] = Seq.empty, firrtlSource: Option[String] = None, customTransforms: Seq[Transform] = List.empty, annotations: List[Annotation] = List.empty, annotationFileNameOverride: String = "", outputAnnotationFileName: String = "", emitOneFilePerModule: Boolean = false, dontCheckCombLoops: Boolean = false, noDCE: Boolean = false, annotationFileNames: List[String] = List.empty, firrtlCircuit: Option[Circuit] = None) extends ComposableOptions with Product with Serializable
The options that firrtl supports in callable component sense
The options that firrtl supports in callable component sense
- inputFileNameOverride
default is targetDir/topName.fir
- outputFileNameOverride
default is targetDir/topName.v the .v is based on the compilerName parameter
- compilerName
which compiler to use
- annotations
annotations to pass to compiler
- Annotations
- @deprecated
- Deprecated
(Since version 1.2) Use a FirrtlOptionsView or construct your own view of an AnnotationSeq
-
sealed
trait
FirrtlExecutionResult extends AnyRef
- Annotations
- @deprecated
- Deprecated
(Since version 1.2) Use FirrtlStage and examine the output AnnotationSeq directly
-
class
FirrtlExecutionSuccess extends FirrtlExecutionResult
Indicates a successful execution of the firrtl compiler, returning the compiled result and the type of compile
Indicates a successful execution of the firrtl compiler, returning the compiled result and the type of compile
- Annotations
- @deprecated
- Deprecated
(Since version 1.2) Use FirrtlStage and examine the output AnnotationSeq directly
-
trait
Gender extends AnyRef
- Annotations
- @deprecated
- Deprecated
(Since version 1.2) Use Flow instead of Gender. This trait will be removed in 1.3
-
trait
HasCommonOptions extends AnyRef
- Annotations
- @deprecated
- Deprecated
(Since version 1.2) Specify command line arguments in an Annotation mixing in HasScoptOptions
-
trait
HasFirrtlOptions extends AnyRef
- Annotations
- @deprecated
- Deprecated
(Since version 1.2) Specify command line arguments in an Annotation mixing in HasScoptOptions
-
abstract
class
HasParser extends AnyRef
- Annotations
- @deprecated
- Deprecated
(Since version 1.2) Use firrtl.options.{ExecutionOptionsManager, TerminateOnExit, DuplicateHandling}
-
type
TargetDirAnnotation = firrtl.options.TargetDirAnnotation
- Annotations
- @deprecated
- Deprecated
(Since version 1.2) Use firrtl.stage.TargetDirAnnotation
Value Members
- implicit def annoSeqToSeq(as: AnnotationSeq): Seq[Annotation]
- implicit def seqToAnnoSeq(xs: Seq[Annotation]): AnnotationSeq
- object Addw extends PrimOp with Product with Serializable
- object AnnotationSeq
-
object
ChirrtlForm extends CircuitForm with Product with Serializable
Chirrtl Form
Chirrtl Form
The form of the circuit emitted by Chisel. Not a true Firrtl form. Includes cmem, smem, and mport IR nodes which enable declaring memories separately form their ports. A "Higher" form than HighForm
See CDefMemory and CDefMPort
- object CircuitState extends Serializable
- object CompilerUtils extends LazyLogging
- object Dshlw extends PrimOp with Product with Serializable
- object DuplexFlow extends Flow with Product with Serializable
- object EmitAllModulesAnnotation extends HasShellOptions with Serializable
- object EmitCircuitAnnotation extends HasShellOptions with Serializable
- object EmptyExpression extends Expression with Product with Serializable
- object ExpKind extends Kind with Product with Serializable
- object FileUtils
-
object
HighForm extends CircuitForm with Product with Serializable
High Form
High Form
As detailed in the Firrtl specification https://github.com/ucb-bar/firrtl/blob/master/spec/spec.pdf
Also see firrtl.ir
- object InstanceKind extends Kind with Product with Serializable
-
object
LowForm extends CircuitForm with Product with Serializable
Low Form
Low Form
The "lowest" form. In addition to the restrictions in MidForm:
- All aggregate types (vector/bundle) must have been removed
- All implicit truncations must be made explicit
- object MInfer extends MPortDir with Product with Serializable
- object MRead extends MPortDir with Product with Serializable
- object MReadWrite extends MPortDir with Product with Serializable
- object MWrite extends MPortDir with Product with Serializable
- object Mappers
- object MemKind extends Kind with Product with Serializable
- object MemoizedHash
-
object
MidForm extends CircuitForm with Product with Serializable
Middle Form
Middle Form
A "lower" form than HighForm with the following restrictions:
- All widths must be explicit
- All whens must be removed
- There can only be a single connection to any element
- object Namespace
- object NodeKind extends Kind with Product with Serializable
- object Parser extends LazyLogging
- object PoisonKind extends Kind with Product with Serializable
- object PortKind extends Kind with Product with Serializable
-
object
PrimOps extends LazyLogging
Definitions and Utility functions for ir.PrimOps
- object RegKind extends Kind with Product with Serializable
- object RenameMap
- object SinkFlow extends Flow with Product with Serializable
- object SourceFlow extends Flow with Product with Serializable
- object Subw extends PrimOp with Product with Serializable
- object UnknownFlow extends Flow with Product with Serializable
-
object
UnknownForm extends CircuitForm with Product with Serializable
Unknown Form
Unknown Form
Often passes may modify a circuit (e.g. InferTypes), but return a circuit in the same form it was given.
For this use case, use UnknownForm. It cannot be compared against other forms.
TODO(azidar): Replace with PreviousForm, which more explicitly encodes this requirement.
- object UnknownKind extends Kind with Product with Serializable
- object Utils extends LazyLogging
- object WDefInstance extends Serializable
- object WGeq
- object WInvalid extends Expression with Product with Serializable
- object WRef extends Serializable
- object WSubField extends Serializable
- object WVoid extends Expression with Product with Serializable
- object WireKind extends Kind with Product with Serializable
- object WrappedExpression
- object WrappedType
- object WrappedWidth
- object bitWidth
- object castRhs
- object connectFields
- object flattenType
- object fromBits
- object getWidth
- object seqCat
-
object
toBits
Given an expression, return an expression consisting of all sub-expressions concatenated (or flattened).
Deprecated Value Members
-
val
TargetDirAnnotation: firrtl.options.TargetDirAnnotation.type
- Annotations
- @deprecated
- Deprecated
(Since version 1.2) Use firrtl.stage.TargetDirAnnotation
-
implicit
def
genderToFlow(gender: Gender): Flow
- Annotations
- @deprecated
- Deprecated
(Since version 1.2) Please migrate from 'Gender' to 'Flow'. This implicit conversion will be removed in 1.3
-
object
BIGENDER extends Gender with Product with Serializable
- Annotations
- @deprecated
- Deprecated
(Since version 1.2) Use DuplexFlow instead of BIGENDER. This case object will be removed in 1.3
-
object
Driver
The driver provides methods to access the firrtl compiler.
The driver provides methods to access the firrtl compiler. Invoke the compiler with either a FirrtlExecutionOption
- Annotations
- @deprecated
- Deprecated
(Since version 1.2) Use firrtl.stage.FirrtlStage
val optionsManager = new ExecutionOptionsManager("firrtl") optionsManager.register( FirrtlExecutionOptionsKey -> new FirrtlExecutionOptions(topName = "Dummy", compilerName = "verilog")) firrtl.Driver.execute(optionsManager)
or a series of command line arguments
, firrtl.Driver.execute(Array("--top-name Dummy --compiler verilog".split(" +"))
each approach has its own endearing aspects
- See also
firrtlTests/DriverSpec.scala in the test directory for a lot more examples
CompilerUtils.mergeTransforms to see how customTransformations are inserted
Examples: -
object
FEMALE extends Gender with Product with Serializable
- Annotations
- @deprecated
- Deprecated
(Since version 1.2) Use SinkFlow instead of FEMALE. This case object will be removed in 1.3
-
object
FIRRTLException extends Serializable
- Annotations
- @deprecated
- Deprecated
(Since version 1.2) External users should use either FirrtlUserException or their own hierarchy
-
object
FirrtlExecutionSuccess
- Annotations
- @deprecated
- Deprecated
(Since version 1.2) Use FirrtlStage and examine the output AnnotationSeq directly
-
object
MALE extends Gender with Product with Serializable
- Annotations
- @deprecated
- Deprecated
(Since version 1.2) Use SourceFlow instead of MALE. This case object will be removed in 1.3
-
object
UNKNOWNGENDER extends Gender with Product with Serializable
- Annotations
- @deprecated
- Deprecated
(Since version 1.2) Use UnknownFlow instead of UNKNOWNGENDER. This case object will be removed in 1.3
This is the documentation for Firrtl.