class InstanceGraph extends AnyRef
A class representing the instance hierarchy of a working IR Circuit
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- InstanceGraph.scala
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asInstanceOf[T0]: T0
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final
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eq(arg0: AnyRef): Boolean
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equals(arg0: Any): Boolean
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def
findInstancesInHierarchy(module: String): Seq[Seq[WDefInstance]]
Finds the absolute paths (each represented by a Seq of instances representing the chain of hierarchy) of all instances of a particular module.
Finds the absolute paths (each represented by a Seq of instances representing the chain of hierarchy) of all instances of a particular module. Note that this includes one implicit instance of the top (main) module of the circuit. If the module is not instantiated within the hierarchy of the top module of the circuit, it will return Nil.
- module
the name of the selected module
- returns
a Seq[ Seq[WDefInstance] ] of absolute instance paths
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lazy val
fullHierarchy: LinkedHashMap[WDefInstance, Seq[Seq[WDefInstance]]]
A list of absolute paths (each represented by a Seq of instances) of all module instances in the Circuit.
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def
getChildrenInstanceMap: Map[OfModule, Map[Instance, OfModule]]
Given a circuit, returns a map from module name to a map in turn mapping instances names to corresponding module names
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def
getChildrenInstanceOfModule: LinkedHashMap[String, LinkedHashSet[(Instance, OfModule)]]
Given a circuit, returns a map from module name to children instance/module firrtl.annotations.TargetTokens
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def
getChildrenInstances: LinkedHashMap[String, LinkedHashSet[WDefInstance]]
Given a circuit, returns a map from module name to children instance/module definitions
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final
def
getClass(): Class[_]
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lazy val
graph: DiGraph[WDefInstance]
A directed graph showing the instance dependencies among modules in the circuit.
A directed graph showing the instance dependencies among modules in the circuit. Every WDefInstance of a module has an edge to every WDefInstance arising from every instance statement in that module.
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def
hashCode(): Int
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final
def
isInstanceOf[T0]: Boolean
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def
lowestCommonAncestor(moduleA: Seq[WDefInstance], moduleB: Seq[WDefInstance]): Seq[WDefInstance]
Finds the lowest common ancestor instances for two module names in a design
- val moduleMap: Map[String, DefModule]
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def
moduleOrder: Seq[DefModule]
Module order from highest module to leaf module
Module order from highest module to leaf module
- returns
sequence of modules in order from top to leaf
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lazy val
modules: Set[OfModule]
The set of all modules in the circuit
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def
ne(arg0: AnyRef): Boolean
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def
notify(): Unit
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final
def
notifyAll(): Unit
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lazy val
reachableModules: Set[OfModule]
The set of all modules in the circuit reachable from the top module
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lazy val
staticInstanceCount: Map[OfModule, Int]
A count of the *static* number of instances of each module.
A count of the *static* number of instances of each module. For any module other than the top (main) module, this is equivalent to the number of inst statements in the circuit instantiating each module, irrespective of the number of times (if any) the enclosing module appears in the hierarchy. Note that top module of the circuit has an associated count of one, even though it is never directly instantiated. Any modules *not* instantiated at all will have a count of zero.
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final
def
synchronized[T0](arg0: ⇒ T0): T0
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def
toString(): String
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- lazy val tour: EulerTour[Seq[WDefInstance]]
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lazy val
unreachableModules: Set[OfModule]
The set of all modules *not* reachable in the circuit
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def
wait(arg0: Long, arg1: Int): Unit
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This is the documentation for Firrtl.