Type Members

1.  class AnalyzeCircuit extends Transform

   AnalyzeCircuit Transform

   AnalyzeCircuit Transform

   Walks Circuit, and records the number of muxes it finds, per module.

   While some compiler frameworks operate on graphs, we represent a Firrtl circuit using a tree representation:

   • A Firrtl Circuit contains a sequence of DefModules.
   • A DefModule contains a sequence of Ports, and maybe a Statement.
   • A Statement can contain other Statements, or Expressions.
   • A Expression can contain other Expressions.

   To visit all Firrtl IR nodes in a circuit, we write functions that recursively walk down this tree. To record statistics, we will pass along the Ledger class and use it when we come across a Mux.

   See the following links for more detailed explanations: Firrtl's IR:

   • https://github.com/ucb-bar/firrtl/wiki/Understanding-Firrtl-Intermediate-Representation Traversing a circuit:
   • https://github.com/ucb-bar/firrtl/wiki/traversing-a-circuit for more Common Pass Idioms:
   • https://github.com/ucb-bar/firrtl/wiki/Common-Pass-Idioms
2.  class Ledger extends AnyRef

   Ledger tracks firrtl.ir.Circuit statistics

   Ledger tracks firrtl.ir.Circuit statistics

   In this lesson, we want to count the number of muxes in each module in our design.

   This Ledger class will be passed along as we walk our circuit, and help us count each Mux we find.

   See lesson1.AnalyzeCircuit