object BackendCompilationUtilities extends LazyLogging
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lazy val
TestDirectory: File
Parent directory for tests
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asInstanceOf[T0]: T0
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def
copyResourceToFile(name: String, file: File): Unit
Copy the contents of a resource to a destination file.
Copy the contents of a resource to a destination file.
- name
the name of the resource
- file
the file to write it into
- def cppToExe(prefix: String, dir: File): ProcessBuilder
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def
createTestDirectory(testName: String): File
Create a test directory
Create a test directory
Will create outer directory called testName then inner directory based on the current time
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equals(arg0: Any): Boolean
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- def executeExpectingFailure(prefix: String, dir: File, assertionMsg: String = ""): Boolean
- def executeExpectingSuccess(prefix: String, dir: File): Boolean
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def
firrtlToVerilog(prefix: String, dir: File): ProcessBuilder
compule chirrtl to verilog by using a separate process
compule chirrtl to verilog by using a separate process
- prefix
basename of the file
- dir
directory where file lives
- returns
true if compiler completed successfully
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logger: Logger
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- def loggingProcessLogger: ProcessLogger
- def makeHarness(template: (String) ⇒ String, post: String)(f: File): File
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toString(): String
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def
verilogToCpp(dutFile: String, dir: File, vSources: Seq[File], cppHarness: File, suppressVcd: Boolean = false, resourceFileName: String = ..., extraCmdLineArgs: Seq[String] = Seq.empty): ProcessBuilder
Generates a Verilator invocation to convert Verilog sources to C++ simulation sources.
Generates a Verilator invocation to convert Verilog sources to C++ simulation sources.
The Verilator prefix will be V$dutFile, and running this will generate C++ sources and headers as well as a makefile to compile them.
Verilator will automatically locate the top-level module as the one among all the files which are not included elsewhere. If multiple ones exist, the compilation will fail.
If the file BlackBoxSourceHelper.fileListName (or an overridden .f resource filename that is specified with the optional resourceFileName parameter) exists in the output directory, it contains a list of source files to be included. Filter out any files in the vSources sequence that are in this file so we don't include the same file multiple times. This complication is an attempt to work-around the fact that clients used to have to explicitly include additional Verilog sources. Now, more of that is automatic.
- dutFile
name of the DUT .v without the .v extension
- dir
output directory
- vSources
list of additional Verilog sources to compile
- cppHarness
C++ testharness to compile/link against
- suppressVcd
specifies if VCD tracing should be suppressed
- resourceFileName
specifies what filename to look for to find a .f file
- extraCmdLineArgs
list of additional command line arguments
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wait(): Unit
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wait(arg0: Long, arg1: Int): Unit
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wait(arg0: Long): Unit
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def
yosysExpectFailure(customTop: String, referenceTop: String, testDir: File, timesteps: Int = 1): Boolean
Creates and runs a Yosys script that creates and runs SAT on a miter circuit.
Creates and runs a Yosys script that creates and runs SAT on a miter circuit. Returns false if SAT succeeds, true otherwise
The custom and reference Verilog files must not contain any modules with the same name otherwise Yosys will not be able to create a miter circuit
- customTop
name of the DUT with custom transforms without the .v extension
- referenceTop
name of the DUT without custom transforms without the .v extension
- testDir
directory containing verilog files
- timesteps
the maximum number of timesteps for Yosys equivalence checking to consider
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def
yosysExpectSuccess(customTop: String, referenceTop: String, testDir: File, timesteps: Int = 1): Boolean
Creates and runs a Yosys script that creates and runs SAT on a miter circuit.
Creates and runs a Yosys script that creates and runs SAT on a miter circuit. Returns true if SAT succeeds, false otherwise
The custom and reference Verilog files must not contain any modules with the same name otherwise Yosys will not be able to create a miter circuit
- customTop
name of the DUT with custom transforms without the .v extension
- referenceTop
name of the DUT without custom transforms without the .v extension
- testDir
directory containing verilog files
- timesteps
the maximum number of timesteps for Yosys equivalence checking to consider
This is the documentation for Firrtl.