Packages

c

firrtl.VerilogEmitter

VerilogRender

class VerilogRender extends AnyRef

Used by getRenderer, it has machinery to produce verilog from IR. Making this a class allows access to particular parts of the verilog emission.

Source
VerilogEmitter.scala
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  1. VerilogRender
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Instance Constructors

  1. new VerilogRender(m: Module, moduleMap: Map[String, DefModule])(implicit writer: Writer)
  2. new VerilogRender(m: Module, moduleMap: Map[String, DefModule], circuitName: String, emissionOptions: EmissionOptions)(implicit writer: Writer)
  3. new VerilogRender(description: Seq[Description], portDescriptions: Map[String, Seq[Description]], m: Module, moduleMap: Map[String, DefModule], circuitName: String, emissionOptions: EmissionOptions)(implicit writer: Writer)

    description

    a description of the start module

    portDescriptions

    a map of port name to description

    m

    the start module

    moduleMap

    a map of modules so submodules can be discovered

    writer

    where rendered information is placed.

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##(): Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. def addFormal(clk: Expression, en: Expression, stmt: Seq[Any], info: Info, msg: StringLit): Unit
  5. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  6. def assign(e: Expression, value: Expression, info: Info): Unit
  7. def assign(e: Expression, infoExpr: InfoExpr): Unit
  8. val assigns: ArrayBuffer[Seq[Any]]
  9. val asyncInitials: ArrayBuffer[Seq[Any]]
  10. val asyncResetAlwaysBlocks: ArrayBuffer[(Expression, Expression, Seq[Any])]
  11. val attachAliases: ArrayBuffer[Seq[Any]]
  12. val attachSynAssigns: ArrayBuffer[Seq[Any]]
  13. def bigIntToVLit(bi: BigInt): String
  14. def build_attribute(attrs: String): Seq[Seq[String]]
  15. def build_comment(desc: String): Seq[Seq[String]]
  16. def build_description(d: Seq[Description]): Seq[Seq[String]]
  17. def build_netlist(s: Statement): Unit
  18. def build_ports(): Unit
  19. def build_streams(s: Statement): Unit
  20. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native() @HotSpotIntrinsicCandidate()
  21. def declare(b: String, n: String, t: Type, info: Info): Unit
  22. def declare(b: String, n: String, t: Type, info: Info, preset: Expression): Any
  23. def declareVectorType(b: String, n: String, tpe: Type, size: BigInt, info: Info, preset: Expression): Unit
  24. def declareVectorType(b: String, n: String, tpe: Type, size: BigInt, info: Info): Unit
  25. val declares: ArrayBuffer[Seq[Any]]
  26. def emitVerilogBind(overrideName: String, body: String): DefModule

    This emits a verilog module that can be bound to a module defined in chisel.

    This emits a verilog module that can be bound to a module defined in chisel. It uses the same machinery as the general emitter in order to insure that parameters signature is exactly the same as the module being bound to

    overrideName

    Override the module name

    body

    the body of the bind module

    returns

    A module constructed from the body

  27. def emit_streams(): Unit
  28. def emit_verilog(): DefModule

    The standard verilog emitter, wraps up everything into the verilog

  29. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  30. def equals(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  31. def formalStatement(op: ir.Formal.Value, cond: Expression): Seq[Any]
  32. val formals: LinkedHashMap[Expression, ArrayBuffer[Seq[Any]]]
  33. def garbageAssign(e: Expression, syn: Expression, garbageCond: Expression, info: Info): ArrayBuffer[Seq[Any]]
  34. final def getClass(): Class[_]
    Definition Classes
    AnyRef → Any
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  35. def hashCode(): Int
    Definition Classes
    AnyRef → Any
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  36. val ifdefDeclares: Map[String, ArrayBuffer[Seq[Any]]]
  37. val ifdefInitials: Map[String, ArrayBuffer[Seq[Any]]]
  38. def initialize(e: Expression, reset: Expression, init: Expression): Any
  39. def initialize_mem(s: DefMemory, opt: MemoryEmissionOption): Unit
  40. val initials: ArrayBuffer[Seq[Any]]
  41. val instdeclares: ArrayBuffer[Seq[Any]]
  42. def invalidAssign(e: Expression): ArrayBuffer[Seq[Any]]
  43. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  44. var maxMemSize: BigInt
  45. val memoryInitials: ArrayBuffer[Seq[Any]]
  46. val moduleTarget: ModuleTarget
  47. val namespace: Namespace
  48. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  49. val netlist: LinkedHashMap[WrappedExpression, InfoExpr]
  50. val noResetAlwaysBlocks: LinkedHashMap[Expression, ArrayBuffer[Seq[Any]]]
  51. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  52. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @HotSpotIntrinsicCandidate()
  53. val portdefs: ArrayBuffer[Seq[Any]]
  54. def printf(str: StringLit, args: Seq[Expression]): Seq[Any]
  55. def rand_string(t: Type): Seq[Any]
  56. def rand_string(t: Type, ifdef: String): Seq[Any]
  57. def rand_string(t: Type, ifdefOpt: Option[String]): Seq[Any]
  58. def regUpdate(r: Expression, clk: Expression, reset: Expression, init: Expression): ArrayBuffer[_ >: Seq[Any] with (Expression, Expression, Seq[Any]) <: Equals]
  59. def simulate(clk: Expression, en: Expression, s: Seq[Any], cond: Option[String], info: Info): ArrayBuffer[Seq[Any]]
  60. val simulates: ArrayBuffer[Seq[Any]]
  61. def stop(ret: Int): Seq[Any]
  62. final def synchronized[T0](arg0: ⇒ T0): T0
    Definition Classes
    AnyRef
  63. def toString(): String
    Definition Classes
    AnyRef → Any
  64. def update(e: Expression, value: Expression, clk: Expression, en: Expression, info: Info): ArrayBuffer[Seq[Any]]
  65. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  66. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... ) @native()
  67. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )

Deprecated Value Members

  1. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] ) @Deprecated
    Deprecated

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