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firrtl.passes.wiring

WiringUtils

object WiringUtils

Source
WiringUtils.scala
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Type Members

  1. type ChildrenMap = HashMap[String, Seq[(String, String)]]
    Annotations
    @deprecated
    Deprecated

    (Since version FIRRTL 1.1.1) Use DiGraph/InstanceGraph

Value Members

  1. final def !=(arg0: Any): Boolean
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  2. final def ##(): Int
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  6. final def eq(arg0: AnyRef): Boolean
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  8. final def getClass(): Class[_]
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  9. def getModuleName(n: Named): String

    Helper script to extract a module name from a named Module or Target

  10. def getType(c: Circuit, module: String, comp: String): Type

    Determine the Type of a specific component

    Determine the Type of a specific component

    c

    the circuit containing the target module

    module

    the module containing the target component

    comp

    the target component

    returns

    the component's type

    Exceptions thrown

    WiringException if the module is not contained in the circuit or if the component is not contained in the module

  11. def hashCode(): Int
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  12. final def isInstanceOf[T0]: Boolean
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  14. final def notify(): Unit
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  15. final def notifyAll(): Unit
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  16. final def synchronized[T0](arg0: ⇒ T0): T0
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  17. def toString(): String
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  18. final def wait(arg0: Long, arg1: Int): Unit
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  19. final def wait(arg0: Long): Unit
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  20. final def wait(): Unit
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Deprecated Value Members

  1. def finalize(): Unit
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    @throws( classOf[java.lang.Throwable] ) @Deprecated
    Deprecated
  2. def getChildrenMap(c: Circuit): ChildrenMap

    Given a circuit, returns a map from module name to children instance/module names

    Given a circuit, returns a map from module name to children instance/module names

    Annotations
    @deprecated
    Deprecated

    (Since version FIRRTL 1.1.1) Use DiGraph/InstanceGraph

  3. def getLineage(childrenMap: ChildrenMap, module: String): Lineage

    Returns a module's lineage, containing all children lineages as well

    Returns a module's lineage, containing all children lineages as well

    Annotations
    @deprecated
    Deprecated

    (Since version FIRRTL 1.1.1) Use DiGraph/InstanceGraph

  4. def sinksToSources(sinks: Seq[Named], source: String, i: InstanceGraph): Map[Seq[WDefInstance], Seq[WDefInstance]]

    Return a map of sink instances to source instances that minimizes distance

    Return a map of sink instances to source instances that minimizes distance

    sinks

    a sequence of sink modules

    source

    the source module

    i

    a graph representing a circuit

    returns

    a map of sink instance names to source instance names

    Annotations
    @deprecated
    Deprecated

    (Since version Firrtl 1.4)

    Exceptions thrown

    WiringException if a sink is equidistant to two sources

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