package passes
- Alphabetic
- Public
- Protected
Type Members
- trait CheckHighFormLike extends AnyRef
- case class DataRef(exp: Expression, source: String, sink: String, mask: String, rdwrite: Boolean) extends Product with Serializable
- class Errors extends AnyRef
- class ExpandWhensAndCheck extends Transform with DependencyAPIMigration
- class InferBinaryPoints extends Pass
- class InferWidths extends Transform with ResolvedAnnotationPaths with DependencyAPIMigration
Infers the widths of all signals with unknown widths
Infers the widths of all signals with unknown widths
Is a global width inference algorithm - Instances of the same module with unknown input port widths will be assigned the largest width of all assignments to each of its instance ports - If you don't want the global inference behavior, then be sure to define all your input widths
Infers the smallest width is larger than all assigned widths to a signal - Note that this means that dummy assignments that are overwritten by last-connect-semantics can still influence width inference - E.g. wire x: UInt x <= UInt<5>(15) x <= UInt<1>(1)
Since width inference occurs before lowering, it infers x's width to be 5 but with an assignment of UInt(1):
wire x: UInt<5> x <= UInt<1>(1)
Uses firrtl.constraint package to infer widths
- case class InlineAnnotation(target: Named) extends SingleTargetAnnotation[Named] with Product with Serializable
Indicates that something should be inlined
- class InlineInstances extends Transform with DependencyAPIMigration with RegisteredTransform
Inline instances as indicated by existing InlineAnnotations
Inline instances as indicated by existing InlineAnnotations
- Note
Only use on legal Firrtl. Specifically, the restriction of instance loops must have been checked, or else this pass can infinitely recurse.
- case class MPort(name: String, clk: Expression) extends Product with Serializable
- case class MPorts(readers: ArrayBuffer[MPort], writers: ArrayBuffer[MPort], readwriters: ArrayBuffer[MPort]) extends Product with Serializable
- trait Pass extends Transform with DependencyAPIMigration
Pass is simple transform that is generally part of a larger Transform Has an UnknownForm, because larger Transform should specify form
- class PassException extends FirrtlUserException
- class PassExceptions extends FirrtlUserException
- class RemoveIntervals extends Pass
Replaces IntervalType with SIntType, three AST walks: 1) Align binary points
Replaces IntervalType with SIntType, three AST walks: 1) Align binary points
- adds shift operators to primop args and connections
- does not affect declaration- or inferred-types 2) Replace Interval DefNode with DefWire + Connect
- You have to do this to capture the smaller bitwidths of nodes that intervals give you. Otherwise, any future InferTypes would re-infer the larger widths on these nodes from SInt width inference rules 3) Replace declaration IntervalType's with SIntType's
- for each declaration:
- remove non-zero binary points b. remove open bounds c. replace with SIntType 3) Run InferTypes
- class TrimIntervals extends Pass
Replaces IntervalType with SIntType, three AST walks: 1) Align binary points
Replaces IntervalType with SIntType, three AST walks: 1) Align binary points
- adds shift operators to primop args and connections
- does not affect declaration- or inferred-types 2) Replace declaration IntervalType's with SIntType's
- for each declaration:
- remove non-zero binary points b. remove open bounds c. replace with SIntType 3) Run InferTypes
- case class WidthGeqConstraintAnnotation(loc: ReferenceTarget, exp: ReferenceTarget) extends Annotation with Product with Serializable
- class WrapWithRemainder extends PassException
Value Members
- object CInferMDir extends Pass
- object CInferTypes extends Pass
- object CheckChirrtl extends Pass with CheckHighFormLike
- object CheckFlows extends Pass
- object CheckHighForm extends Pass with CheckHighFormLike
- object CheckInitialization extends Pass
Reports errors for any references that are not fully initialized
Reports errors for any references that are not fully initialized
- Note
This pass looks for firrtl.WVoids left behind by ExpandWhens
,Assumes single connection (ie. no last connect semantics)
- object CheckTypes extends Pass
- object CheckWidths extends Pass
- object CommonSubexpressionElimination extends Transform with HasShellOptions with DependencyAPIMigration
- object ConvertFixedToSInt extends Pass
Replaces FixedType with SIntType, and correctly aligns all binary points
- object ExpandConnects extends Pass
- object ExpandWhens extends Pass
Expand Whens
Expand Whens
This pass does the following things: $ - Remove last connect semantics $ - Remove conditional blocks $ - Eliminate concept of scoping $ - Consolidate attaches
- Note
Assumes bulk connects and isInvalids have been expanded
,Assumes all references are declared
- object InferTypes extends Pass
- object InferWidths
- object InlineInstances
- object LegalizeConnects extends Pass
Ensures that all connects + register inits have the same bit-width on the rhs and the lhs.
Ensures that all connects + register inits have the same bit-width on the rhs and the lhs. The rhs is padded or bit-extacted to fit the width of the lhs.
- Note
technically, width(rhs) > width(lhs) is not legal firrtl, however, we do not error for historic reasons.
- object LowerTypes extends Transform with DependencyAPIMigration
Flattens Bundles and Vecs.
Flattens Bundles and Vecs. - Some implicit bundle types remain, but with a limited depth:
- the type of a memory is still a bundle with depth 2 (mem -> port -> field), see MemPortUtils.memType
- the type of a module instance is still a bundle with depth 1 (instance -> port)
- object MemPortUtils
- case object NoCommonSubexpressionEliminationAnnotation extends NoTargetAnnotation with Product with Serializable
Indicate that CommonSubexpressionElimination should not be run
- object PadWidths extends Pass
- object PullMuxes extends Pass
- object RemoveAccesses extends Pass
Removes all firrtl.WSubAccess from circuit
- object RemoveCHIRRTL extends Transform with DependencyAPIMigration
- object RemoveEmpty extends Pass with DependencyAPIMigration
- object RemoveValidIf extends Pass
Remove ValidIf and replace IsInvalid with a connection to zero
- object ReplaceAccesses extends Pass
Replaces constant firrtl.WSubAccess with firrtl.WSubIndex TODO Fold in to High Firrtl Const Prop
- object ResolveFlows extends Pass
- object ResolveKinds extends Pass
- object SplitExpressions extends Pass
- object VerilogPrep extends Pass
Makes changes to the Firrtl AST to make Verilog emission easier
Makes changes to the Firrtl AST to make Verilog emission easier
- For each instance, adds wires to connect to each port
- Note that no Namespace is required because Uniquify ensures that there will be no collisions with the lowered names of instance ports - Also removes Attaches where a single Port OR Wire connects to 1 or more instance ports
- These are expressed in the portCons of WDefInstConnectors
- Note
The result of this pass is NOT legal Firrtl
- object ZeroLengthVecs extends Pass
Handles dynamic accesses to zero-length vectors.
Handles dynamic accesses to zero-length vectors.
- Note
Removes assignments that use a zero-length vector as a sink
,Removes signals resulting from accesses to a zero-length vector from attach groups
,Removes attaches that become degenerate after zero-length-accessor removal
,Replaces "source" references to elements of zero-length vectors with always-invalid validif
- object ZeroWidth extends Transform with DependencyAPIMigration
- object createMask
- object toBitMask
Given a mask, return a bitmask corresponding to the desired datatype.
Given a mask, return a bitmask corresponding to the desired datatype. Requirements:
- The mask type and datatype must be equivalent, except any ground type in datatype must be matched by a 1-bit wide UIntType.
- The mask must be a reference, subfield, or subindex The bitmask is a series of concatenations of the single mask bit over the length of the corresponding ground type, e.g.:
wire mask: {x: UInt<1>, y: UInt<1>} wire data: {x: UInt<2>, y: SInt<2>} // this would return: cat(cat(mask.x, mask.x), cat(mask.y, mask.y))
Deprecated Value Members
- object ToWorkingIR extends Pass
- Annotations
- @deprecated
- Deprecated
(Since version FIRRTL 1.4.2) This pass is an identity transform. For an equivalent dependency, use firrtl.stage.forms.MinimalHighForm
- object Uniquify extends Transform with DependencyAPIMigration
Resolve name collisions that would occur in the old LowerTypes pass
Resolve name collisions that would occur in the old LowerTypes pass
- Annotations
- @deprecated
- Deprecated
(Since version FIRRTL 1.4.0) Uniquify is now part of LowerTypes
wire a = { b, c }[2] wire a_0
This lowers to:
wire a__0_b wire a__0_c wire a__1_b wire a__1_c wire a_0
There wouldn't be a collision even if we didn't map a -> a_, but there WOULD be collisions in references a[0] and a_0 so we still have to rename a
- Note
Must be run after InferTypes because ir.DefNodes need type
Example: - object VerilogModulusCleanup extends Pass
Verilog has the width of (a % b) = Max(W(a), W(b)) FIRRTL has the width of (a % b) = Min(W(a), W(b)), which makes more sense, but nevertheless is a problem when emitting verilog
Verilog has the width of (a % b) = Max(W(a), W(b)) FIRRTL has the width of (a % b) = Min(W(a), W(b)), which makes more sense, but nevertheless is a problem when emitting verilog
This pass finds every instance of (a % b) and: 1) adds a temporary node equal to (a % b) with width Max(W(a), W(b)) 2) replaces the reference to (a % b) with a bitslice of the temporary node to get back down to width Min(W(a), W(b))
This is technically incorrect firrtl, but allows the verilog emitter to emit correct verilog without needing to add temporary nodes
- Annotations
- @deprecated
- Deprecated
(Since version FIRRTL 1.5.2) This pass's functionality has been moved to LegalizeVerilog
This is the documentation for Firrtl.