c

dspblocks

TLDspQueue

class TLDspQueue extends TLRegisterRouter[TLRegBundle[Int], TLRegModule[Int, TLRegBundle[Int]] with DspQueueImp[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle]] with DspQueue[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle] with TLDspBlock

Linear Supertypes
TLDspBlock, DspQueue[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle], DspBlock[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle], TLRegisterRouter[TLRegBundle[Int], TLRegModule[Int, TLRegBundle[Int]] with DspQueueImp[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle]], TLRegisterRouterBase, LazyModule, AnyRef, Any
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  2. By Inheritance
Inherited
  1. TLDspQueue
  2. TLDspBlock
  3. DspQueue
  4. DspBlock
  5. TLRegisterRouter
  6. TLRegisterRouterBase
  7. LazyModule
  8. AnyRef
  9. Any
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Visibility
  1. Public
  2. All

Instance Constructors

  1. new TLDspQueue(depth: Int, baseAddr: BigInt = 0, devname: String = "vqueue", concurrency: Int = 1)(implicit p: Parameters)

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##(): Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. val address: AddressSet
    Definition Classes
    TLRegisterRouterBase
  5. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  6. val base: BigInt
    Definition Classes
    TLRegisterRouter
  7. val baseAddr: BigInt
  8. val beatBytes: Int
    Definition Classes
    TLRegisterRouter
  9. var children: List[LazyModule]
    Attributes
    protected[freechips.rocketchip.diplomacy]
    Definition Classes
    LazyModule
  10. lazy val className: String
    Definition Classes
    LazyModule
  11. def clone(): AnyRef
    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @native() @throws( ... )
  12. val concurrency: Int
    Definition Classes
    TLRegisterRouter
  13. val depth: Int

    Depth of queue

    Depth of queue

    Definition Classes
    TLDspQueueDspQueue
  14. lazy val desiredName: String
    Definition Classes
    LazyModule
  15. val devcompat: Seq[String]
    Definition Classes
    TLRegisterRouter
  16. val device: SimpleDevice
    Definition Classes
    TLRegisterRouterBase
  17. val devname: String
    Definition Classes
    TLRegisterRouter
  18. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  19. def equals(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  20. val executable: Boolean
    Definition Classes
    TLRegisterRouter
  21. def extraResources(resources: ResourceBindings): Map[String, Seq[ResourceValue]]
    Definition Classes
    TLRegisterRouterBase
  22. def finalize(): Unit
    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] )
  23. def getChildren: List[LazyModule]
    Definition Classes
    LazyModule
  24. final def getClass(): Class[_]
    Definition Classes
    AnyRef → Any
    Annotations
    @native()
  25. lazy val graphML: String
    Definition Classes
    LazyModule
  26. def hashCode(): Int
    Definition Classes
    AnyRef → Any
    Annotations
    @native()
  27. var inModuleBody: List[() ⇒ Unit]
    Attributes
    protected[freechips.rocketchip.diplomacy]
    Definition Classes
    LazyModule
  28. var info: SourceInfo
    Attributes
    protected[freechips.rocketchip.diplomacy]
    Definition Classes
    LazyModule
  29. lazy val instanceName: String
    Definition Classes
    LazyModule
  30. val interrupts: Int
    Definition Classes
    TLRegisterRouter
  31. val intnode: IntSourceNode
    Definition Classes
    TLRegisterRouterBase
  32. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  33. def line: String
    Definition Classes
    LazyModule
  34. val mem: Some[TLRegisterNode]

    Diplmatic node for memory interface Some blocks might not need memory mapping, so this is an Option[]

    Diplmatic node for memory interface Some blocks might not need memory mapping, so this is an Option[]

    Definition Classes
    TLDspQueueDspBlock
  35. lazy val module: TLRegModule[Int, TLRegBundle[Int]] with DspQueueImp[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
    Definition Classes
    TLRegisterRouter → LazyModule
  36. lazy val moduleName: String
    Definition Classes
    LazyModule
  37. def name: String
    Definition Classes
    LazyModule
  38. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  39. val node: TLRegisterNode
    Definition Classes
    TLRegisterRouterBase
  40. def nodeIterator(iterfunc: (LazyModule) ⇒ Unit): Unit
    Definition Classes
    LazyModule
  41. var nodes: List[BaseNode]
    Attributes
    protected[freechips.rocketchip.diplomacy]
    Definition Classes
    LazyModule
  42. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native()
  43. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native()
  44. def omitGraphML: Boolean
    Definition Classes
    LazyModule
  45. implicit val p: Parameters
    Definition Classes
    LazyModule
  46. val parent: Option[LazyModule]
    Attributes
    protected[freechips.rocketchip.diplomacy]
    Definition Classes
    LazyModule
  47. def parents: Seq[LazyModule]
    Definition Classes
    LazyModule
  48. lazy val pathName: String
    Definition Classes
    LazyModule
  49. val size: BigInt
    Definition Classes
    TLRegisterRouter
  50. val streamNode: AXI4StreamIdentityNode

    Diplomatic node for AXI4-Stream interfaces

    Diplomatic node for AXI4-Stream interfaces

    Definition Classes
    DspQueueDspBlock
  51. def suggestName(x: Option[String]): TLDspQueue.this.type
    Definition Classes
    LazyModule
  52. def suggestName(x: String): TLDspQueue.this.type
    Definition Classes
    LazyModule
  53. lazy val suggestedName: String
    Definition Classes
    LazyModule
  54. final def synchronized[T0](arg0: ⇒ T0): T0
    Definition Classes
    AnyRef
  55. def toString(): String
    Definition Classes
    AnyRef → Any
  56. val undefZero: Boolean
    Definition Classes
    TLRegisterRouter
  57. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  58. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  59. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @throws( ... )

Inherited from TLDspBlock

Inherited from DspQueue[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle]

Inherited from DspBlock[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle]

Inherited from TLRegisterRouter[TLRegBundle[Int], TLRegModule[Int, TLRegBundle[Int]] with DspQueueImp[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle]]

Inherited from TLRegisterRouterBase

Inherited from LazyModule

Inherited from AnyRef

Inherited from Any

Ungrouped