| Interface | Description |
|---|---|
| AMD64Assembler.VexRRIOp |
| Class | Description |
|---|---|
| AMD64Address |
Represents an address in target machine memory, specified via some combination of a base
register, an index register, a displacement and a scale.
|
| AMD64AsmOptions | |
| AMD64Assembler |
This class implements an assembler that can encode most X86 instructions.
|
| AMD64Assembler.AMD64BinaryArithmetic |
Arithmetic operation with operand order of RM, MR or MI.
|
| AMD64Assembler.AMD64ImmOp |
Base class for AMD64 opcodes with immediate operands.
|
| AMD64Assembler.AMD64MIOp |
Opcodes with operand order of MI.
|
| AMD64Assembler.AMD64MOp |
Opcodes with operand order of M.
|
| AMD64Assembler.AMD64MROp |
Opcode with operand order of MR.
|
| AMD64Assembler.AMD64Op |
Base class for AMD64 opcodes.
|
| AMD64Assembler.AMD64RMIOp |
Opcodes with operand order of RMI.
|
| AMD64Assembler.AMD64RMOp |
Opcode with operand order of RM.
|
| AMD64Assembler.AMD64RROp |
Opcode with operand order of either RM or MR for 2 address forms.
|
| AMD64Assembler.AMD64Shift |
Shift operation with operand order of M1, MC or MI.
|
| AMD64Assembler.SSEOp | |
| AMD64Assembler.VexFloatCompareOp |
VEX-encoded comparison operation with an operand order of RVMI.
|
| AMD64Assembler.VexGeneralPurposeRMOp | |
| AMD64Assembler.VexGeneralPurposeRMVOp | |
| AMD64Assembler.VexGeneralPurposeRVMOp | |
| AMD64Assembler.VexMaskMoveOp | |
| AMD64Assembler.VexMoveOp |
VEX-encoded move instructions.
|
| AMD64Assembler.VexMRIOp |
VEX-encoded instructions with an operand order of MRI.
|
| AMD64Assembler.VexOp |
Base class for VEX-encoded instructions.
|
| AMD64Assembler.VexRMIOp |
VEX-encoded instructions with an operand order of RMI.
|
| AMD64Assembler.VexRMOp |
VEX-encoded instructions with an operand order of RM.
|
| AMD64Assembler.VexRROp |
VEX-encoded instructions with an operand order of RM, but the M operand must be a register.
|
| AMD64Assembler.VexRVMIOp |
VEX-encoded instructions with an operand order of RVMI.
|
| AMD64Assembler.VexRVMOp |
VEX-encoded instructions with an operand order of RVM.
|
| AMD64Assembler.VexRVMROp |
VEX-encoded instructions with an operand order of RVMR.
|
| AMD64Assembler.VexShiftOp |
VEX-encoded shift instructions with an operand order of either RVM or VMI.
|
| AMD64BaseAssembler |
This class implements an assembler that can encode most X86 instructions.
|
| AMD64BaseAssembler.AddressDisplacementAnnotation |
Annotation that stores additional information about the displacement of a
placeholder address that needs patching. |
| AMD64BaseAssembler.EVEXPrefixConfig | |
| AMD64BaseAssembler.ImmediateOperandAnnotation |
Annotation that stores additional information about the immediate operand, e.g., of a call
instruction, that needs patching.
|
| AMD64BaseAssembler.OperandDataAnnotation | |
| AMD64BaseAssembler.VEXPrefixConfig | |
| AMD64MacroAssembler |
This class implements commonly used X86 code patterns.
|
| AVXKind |
Helper methods for dealing with AVX and SSE
AMD64Kinds. |
| Enum | Description |
|---|---|
| AMD64Address.Scale |
A scaling factor used in the SIB addressing mode.
|
| AMD64Assembler.ConditionFlag |
The x86 condition codes used for conditional jumps/moves.
|
| AMD64Assembler.VexFloatCompareOp.Predicate | |
| AMD64BaseAssembler.EVEXTuple |
EVEX-encoded instructions use a compressed displacement scheme by multiplying disp8 with a
scaling factor N depending on the tuple type and the vector length.
|
| AMD64BaseAssembler.OperandSize |
The x86 operand sizes.
|
| AVXKind.AVXSize |