VhdlBase

Value Members

1. final def !=(arg0: Any): Boolean

   

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2. final def ##(): Int

   

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3. final def ==(arg0: Any): Boolean

   

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4. final def asInstanceOf[T0]: T0

   

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5. def clone(): AnyRef

   

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   protected[java.lang]

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6. def emitClockEdge(clock: Bool, edgeKind: EdgeKind): String

   

7. def emitDataType(node: Node, constrained: Boolean = true): String

   

8. def emitDirection(baseType: BaseType): String

   

9. def emitEnumLiteral[T <: SpinalEnum](enum: SpinalEnumElement[T], encoding: SpinalEnumEncoding): String

   

10. def emitEnumType(enum: SpinalEnum, encoding: SpinalEnumEncoding): String

    

11. def emitEnumType[T <: SpinalEnum](enum: SpinalEnumCraft[T]): String

    

12. def emitLibrary(ret: StringBuilder): Unit

    

13. def emitRange(node: Widthable): String

    

14. def emitReference(node: Node): String

    

15. def emitSignal(ref: Node, typeNode: Node): String

    

16. var enumPackageName: String

    

17. final def eq(arg0: AnyRef): Boolean

    

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18. def equals(arg0: Any): Boolean

    

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19. def finalize(): Unit

    

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    protected[java.lang]

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20. def getAsyncProcesses(component: Component, merge: Boolean = true): Seq[Process]

    

    Definition Classes

    VhdlVerilogBase

21. final def getClass(): Class[_]

    

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22. def getSensitivity(nodes: Iterable[Node], includeNodes: Boolean): Set[Node]

    

    Definition Classes

    VhdlVerilogBase

23. def hashCode(): Int

    

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24. final def isInstanceOf[T0]: Boolean

    

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25. def isReferenceable(node: Node): Boolean

    

    Definition Classes

    VhdlVerilogBase

26. final def ne(arg0: AnyRef): Boolean

    

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27. final def notify(): Unit

    

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28. final def notifyAll(): Unit

    

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29. var packageName: String

    

30. final def synchronized[T0](arg0: ⇒ T0): T0

    

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31. def toString(): String

    

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32. final def wait(): Unit

    

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33. final def wait(arg0: Long, arg1: Int): Unit

    

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34. final def wait(arg0: Long): Unit

    

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