case class SpinalConfig(mode: SpinalMode = null, debug: Boolean = false, debugComponents: HashSet[Class[_]] = mutable.HashSet[Class[_]](), keepAll: Boolean = false, defaultConfigForClockDomains: ClockDomainConfig = ClockDomainConfig(), onlyStdLogicVectorAtTopLevelIo: Boolean = false, defaultClockDomainFrequency: IClockDomainFrequency = UnknownFrequency(), targetDirectory: String = ".", oneFilePerComponent: Boolean = false, netlistFileName: String = null, dumpWave: DumpWaveConfig = null, globalPrefix: String = "", anonymSignalPrefix: String = null, device: Device = Device(), inlineRom: Boolean = false, genVhdlPkg: Boolean = true, verbose: Boolean = false, mergeAsyncProcess: Boolean = true, asyncResetCombSensitivity: Boolean = false, anonymSignalUniqueness: Boolean = false, phasesInserters: ArrayBuffer[(ArrayBuffer[Phase]) ⇒ Unit] = ..., transformationPhases: ArrayBuffer[Phase] = ArrayBuffer[Phase](), memBlackBoxers: ArrayBuffer[Phase] = ..., rtlHeader: String = null) extends Product with Serializable
Spinal configuration for the generation of the RTL
Linear Supertypes
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Instance Constructors
- new SpinalConfig(mode: SpinalMode = null, debug: Boolean = false, debugComponents: HashSet[Class[_]] = mutable.HashSet[Class[_]](), keepAll: Boolean = false, defaultConfigForClockDomains: ClockDomainConfig = ClockDomainConfig(), onlyStdLogicVectorAtTopLevelIo: Boolean = false, defaultClockDomainFrequency: IClockDomainFrequency = UnknownFrequency(), targetDirectory: String = ".", oneFilePerComponent: Boolean = false, netlistFileName: String = null, dumpWave: DumpWaveConfig = null, globalPrefix: String = "", anonymSignalPrefix: String = null, device: Device = Device(), inlineRom: Boolean = false, genVhdlPkg: Boolean = true, verbose: Boolean = false, mergeAsyncProcess: Boolean = true, asyncResetCombSensitivity: Boolean = false, anonymSignalUniqueness: Boolean = false, phasesInserters: ArrayBuffer[(ArrayBuffer[Phase]) ⇒ Unit] = ..., transformationPhases: ArrayBuffer[Phase] = ArrayBuffer[Phase](), memBlackBoxers: ArrayBuffer[Phase] = ..., rtlHeader: String = null)
Value Members
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final
def
!=(arg0: Any): Boolean
- Definition Classes
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final
def
##(): Int
- Definition Classes
- AnyRef → Any
-
final
def
==(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- def addStandardMemBlackboxing(policy: MemBlackboxingPolicy): SpinalConfig.this.type
- def addTransformationPhase(phase: Phase): SpinalConfig
- val anonymSignalPrefix: String
- val anonymSignalUniqueness: Boolean
- def apply[T <: Component](gen: ⇒ T): SpinalReport[T]
- def applyToGlobalData(globalData: GlobalData): Unit
-
final
def
asInstanceOf[T0]: T0
- Definition Classes
- Any
- val asyncResetCombSensitivity: Boolean
-
def
clone(): AnyRef
- Attributes
- protected[java.lang]
- Definition Classes
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- Annotations
- @native() @throws( ... )
- val debugComponents: HashSet[Class[_]]
- val defaultClockDomainFrequency: IClockDomainFrequency
- val defaultConfigForClockDomains: ClockDomainConfig
- val device: Device
- def dumpWave(depth: Int = 0, vcdPath: String = "wave.vcd"): SpinalConfig
- val dumpWave: DumpWaveConfig
-
final
def
eq(arg0: AnyRef): Boolean
- Definition Classes
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-
def
finalize(): Unit
- Attributes
- protected[java.lang]
- Definition Classes
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- Annotations
- @throws( classOf[java.lang.Throwable] )
- val genVhdlPkg: Boolean
- def generate[T <: Component](gen: ⇒ T): SpinalReport[T]
- def generateSystemVerilog[T <: Component](gen: ⇒ T): SpinalReport[T]
- def generateVerilog[T <: Component](gen: ⇒ T): SpinalReport[T]
- def generateVhdl[T <: Component](gen: ⇒ T): SpinalReport[T]
-
final
def
getClass(): Class[_]
- Definition Classes
- AnyRef → Any
- Annotations
- @native()
- val globalPrefix: String
- val inlineRom: Boolean
-
final
def
isInstanceOf[T0]: Boolean
- Definition Classes
- Any
- def isSystemVerilog: Boolean
- val keepAll: Boolean
- val memBlackBoxers: ArrayBuffer[Phase]
- val mergeAsyncProcess: Boolean
- val mode: SpinalMode
-
final
def
ne(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- val netlistFileName: String
-
final
def
notify(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native()
-
final
def
notifyAll(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native()
- val oneFilePerComponent: Boolean
- val onlyStdLogicVectorAtTopLevelIo: Boolean
- val phasesInserters: ArrayBuffer[(ArrayBuffer[Phase]) ⇒ Unit]
- val rtlHeader: String
-
final
def
synchronized[T0](arg0: ⇒ T0): T0
- Definition Classes
- AnyRef
- val targetDirectory: String
- val transformationPhases: ArrayBuffer[Phase]
- val verbose: Boolean
-
final
def
wait(): Unit
- Definition Classes
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- @throws( ... )
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final
def
wait(arg0: Long, arg1: Int): Unit
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- @throws( ... )
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final
def
wait(arg0: Long): Unit
- Definition Classes
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- @native() @throws( ... )
Deprecated Value Members
-
val
debug: Boolean
- Annotations
- @deprecated
- Deprecated