Packages

case class SpinalConfig(mode: SpinalMode = null, debug: Boolean = false, debugComponents: HashSet[Class[_]] = mutable.HashSet[Class[_]](), keepAll: Boolean = false, defaultConfigForClockDomains: ClockDomainConfig = ClockDomainConfig(), onlyStdLogicVectorAtTopLevelIo: Boolean = false, defaultClockDomainFrequency: IClockDomainFrequency = UnknownFrequency(), targetDirectory: String = ".", oneFilePerComponent: Boolean = false, netlistFileName: String = null, dumpWave: DumpWaveConfig = null, globalPrefix: String = "", anonymSignalPrefix: String = null, device: Device = Device(), inlineRom: Boolean = false, genVhdlPkg: Boolean = true, verbose: Boolean = false, mergeAsyncProcess: Boolean = true, asyncResetCombSensitivity: Boolean = false, anonymSignalUniqueness: Boolean = false, phasesInserters: ArrayBuffer[(ArrayBuffer[Phase]) ⇒ Unit] = ..., transformationPhases: ArrayBuffer[Phase] = ArrayBuffer[Phase](), memBlackBoxers: ArrayBuffer[Phase] = ..., rtlHeader: String = null) extends Product with Serializable

Spinal configuration for the generation of the RTL

Linear Supertypes
Serializable, Serializable, Product, Equals, AnyRef, Any
Ordering
  1. Alphabetic
  2. By Inheritance
Inherited
  1. SpinalConfig
  2. Serializable
  3. Serializable
  4. Product
  5. Equals
  6. AnyRef
  7. Any
  1. Hide All
  2. Show All
Visibility
  1. Public
  2. All

Instance Constructors

  1. new SpinalConfig(mode: SpinalMode = null, debug: Boolean = false, debugComponents: HashSet[Class[_]] = mutable.HashSet[Class[_]](), keepAll: Boolean = false, defaultConfigForClockDomains: ClockDomainConfig = ClockDomainConfig(), onlyStdLogicVectorAtTopLevelIo: Boolean = false, defaultClockDomainFrequency: IClockDomainFrequency = UnknownFrequency(), targetDirectory: String = ".", oneFilePerComponent: Boolean = false, netlistFileName: String = null, dumpWave: DumpWaveConfig = null, globalPrefix: String = "", anonymSignalPrefix: String = null, device: Device = Device(), inlineRom: Boolean = false, genVhdlPkg: Boolean = true, verbose: Boolean = false, mergeAsyncProcess: Boolean = true, asyncResetCombSensitivity: Boolean = false, anonymSignalUniqueness: Boolean = false, phasesInserters: ArrayBuffer[(ArrayBuffer[Phase]) ⇒ Unit] = ..., transformationPhases: ArrayBuffer[Phase] = ArrayBuffer[Phase](), memBlackBoxers: ArrayBuffer[Phase] = ..., rtlHeader: String = null)

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##(): Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. def addStandardMemBlackboxing(policy: MemBlackboxingPolicy): SpinalConfig.this.type
  5. def addTransformationPhase(phase: Phase): SpinalConfig
  6. val anonymSignalPrefix: String
  7. val anonymSignalUniqueness: Boolean
  8. def apply[T <: Component](gen: ⇒ T): SpinalReport[T]
  9. def applyToGlobalData(globalData: GlobalData): Unit
  10. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  11. val asyncResetCombSensitivity: Boolean
  12. def clone(): AnyRef
    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @native() @throws( ... )
  13. val debugComponents: HashSet[Class[_]]
  14. val defaultClockDomainFrequency: IClockDomainFrequency
  15. val defaultConfigForClockDomains: ClockDomainConfig
  16. val device: Device
  17. def dumpWave(depth: Int = 0, vcdPath: String = "wave.vcd"): SpinalConfig
  18. val dumpWave: DumpWaveConfig
  19. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  20. def finalize(): Unit
    Attributes
    protected[java.lang]
    Definition Classes
    AnyRef
    Annotations
    @throws( classOf[java.lang.Throwable] )
  21. val genVhdlPkg: Boolean
  22. def generate[T <: Component](gen: ⇒ T): SpinalReport[T]
  23. def generateSystemVerilog[T <: Component](gen: ⇒ T): SpinalReport[T]
  24. def generateVerilog[T <: Component](gen: ⇒ T): SpinalReport[T]
  25. def generateVhdl[T <: Component](gen: ⇒ T): SpinalReport[T]
  26. final def getClass(): Class[_]
    Definition Classes
    AnyRef → Any
    Annotations
    @native()
  27. val globalPrefix: String
  28. val inlineRom: Boolean
  29. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  30. def isSystemVerilog: Boolean
  31. val keepAll: Boolean
  32. val memBlackBoxers: ArrayBuffer[Phase]
  33. val mergeAsyncProcess: Boolean
  34. val mode: SpinalMode
  35. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  36. val netlistFileName: String
  37. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native()
  38. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native()
  39. val oneFilePerComponent: Boolean
  40. val onlyStdLogicVectorAtTopLevelIo: Boolean
  41. val phasesInserters: ArrayBuffer[(ArrayBuffer[Phase]) ⇒ Unit]
  42. val rtlHeader: String
  43. final def synchronized[T0](arg0: ⇒ T0): T0
    Definition Classes
    AnyRef
  44. val targetDirectory: String
  45. val transformationPhases: ArrayBuffer[Phase]
  46. val verbose: Boolean
  47. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  48. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws( ... )
  49. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @throws( ... )

Deprecated Value Members

  1. val debug: Boolean
    Annotations
    @deprecated
    Deprecated

Inherited from Serializable

Inherited from Serializable

Inherited from Product

Inherited from Equals

Inherited from AnyRef

Inherited from Any

Ungrouped