sealed class SyncReadMem[T <: Data] extends MemBase[T]
A sequential/synchronous-read, sequential/synchronous-write memory.
Writes take effect on the rising clock edge after the request. Reads return data on the rising edge after the request. Read-after-write behavior (when a read and write to the same address are requested on the same cycle) is undefined.
- Note
when multiple conflicting writes are performed on a Mem element, the result is undefined (unlike Vec, where the last assignment wins)
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def
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final
def
==(arg0: Any): Boolean
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macro
def
apply(x: UInt): T
Creates a read/write accessor into the memory with dynamic addressing.
Creates a read/write accessor into the memory with dynamic addressing. See the class documentation of the memory for more detailed information.
- Definition Classes
- MemBase
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macro
def
apply(x: Int): T
Creates a read accessor into the memory with static addressing.
Creates a read accessor into the memory with static addressing. See the class documentation of the memory for more detailed information.
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- MemBase
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macro
def
apply(x: BigInt): T
Creates a read accessor into the memory with static addressing.
Creates a read accessor into the memory with static addressing. See the class documentation of the memory for more detailed information.
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final
def
asInstanceOf[T0]: T0
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def
circuitName: String
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def
clone(): AnyRef
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def
do_apply(idx: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T
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def
do_apply(idx: Int)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T
- Definition Classes
- MemBase
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def
do_apply(idx: BigInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T
- Definition Classes
- MemBase
- def do_read(addr: UInt, enable: Bool)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T
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def
do_read(idx: UInt)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T
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final
def
eq(arg0: AnyRef): Boolean
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instanceName: String
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def
isInstanceOf[T0]: Boolean
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val
length: BigInt
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def
parentPathName: String
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def
pathName: String
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- macro def read(x: UInt, en: Bool): T
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macro
def
read(x: UInt): T
Creates a read accessor into the memory with dynamic addressing.
Creates a read accessor into the memory with dynamic addressing. See the class documentation of the memory for more detailed information.
- Definition Classes
- MemBase
- val readUnderWrite: ReadUnderWrite
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def
suggestName(name: ⇒ String): SyncReadMem.this.type
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final
def
synchronized[T0](arg0: ⇒ T0): T0
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val
t: T
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final
def
toAbsoluteTarget: ReferenceTarget
Returns a FIRRTL IsMember that refers to the absolute path to this object in the elaborated hardware graph
Returns a FIRRTL IsMember that refers to the absolute path to this object in the elaborated hardware graph
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final
def
toNamed: ComponentName
Returns a FIRRTL ComponentName that references this object
Returns a FIRRTL ComponentName that references this object
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Should not be called until circuit elaboration is complete
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def
toString(): String
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final
def
toTarget: ReferenceTarget
Returns a FIRRTL ReferenceTarget that references this object
Returns a FIRRTL ReferenceTarget that references this object
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- Note
Should not be called until circuit elaboration is complete
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final
def
wait(): Unit
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def
wait(arg0: Long, arg1: Int): Unit
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final
def
wait(arg0: Long): Unit
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def
write(idx: UInt, data: T, mask: Seq[Bool])(implicit evidence: <:<[T, Vec[_]], compileOptions: CompileOptions): Unit
Creates a masked write accessor into the memory.
Creates a masked write accessor into the memory.
- idx
memory element index to write into
- data
new data to write
- mask
write mask as a Seq of Bool: a write to the Vec element in memory is only performed if the corresponding mask index is true.
- Definition Classes
- MemBase
- Note
this is only allowed if the memory's element data type is a Vec
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def
write(idx: UInt, data: T)(implicit compileOptions: CompileOptions): Unit
Creates a write accessor into the memory.
Creates a write accessor into the memory.
- idx
memory element index to write into
- data
new data to write
- Definition Classes
- MemBase