chiseltest
package chiseltest
Basic interfaces and implicit conversions for testers2
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- package coverage
- package experimental
Your warranty is now void.
Your warranty is now void.
experimental contains cutting edge features that are, well, experimental, and carry no expectation of long-term support. We may break experimental APIs at any time. These may not work as expected, or may have unforeseen side effects, or may be powerful yet dangerous.
You have been warned.
- package formal
- package internal
- package iotesters
- package simulator
Type Members
- class ChiselAssertionError extends Exception
Indicates that a Chisel
assert(...)
orassume(...)
statement has failed. - trait ChiselScalatestTester extends Assertions with TestSuiteMixin with TestEnvInterface with HasTestName
- trait ChiselUtestTester extends TestSuite with TestEnvInterface
Using utest as test framework
Using utest as test framework
// define test spec in trait trait HasTestChipSpec { import chisel3.tester._ def testChipSpec(dut: TestChip): Unit = { c => // body of the unit test, c is a reference c.io.input.poke(1.U) c.io.output.expect(2.U) } } object SomeCircuitSpecTester extends ChiselUtestTester with HasSomeCircuitSpec { // define test by Tests macro val tests: Tests = Tests { // invoke test with test(""){} test("comments or name to a test"){ // test function runs here testCircuit(new SomeCircuit, Seq(WriteVcdAnnotation))(SomeCircuitSpec) } } }
- class ClockResolutionException extends Exception
- class DecoupledDriver[T <: Data] extends AnyRef
- trait HasTestName extends AnyRef
- class LiteralTypeException extends Exception
- class NonLiteralValueError extends Exception
Indicates that a value used in a poke/expect is not a literal.
Indicates that a value used in a poke/expect is not a literal. It could be hardware or a DontCare which is only allowed when using pokePartial/expectPartial.
- class NotLiteralException extends Exception
- sealed class Region extends AnyRef
Base class for regions, akin to Verilog regions for ordering events between threads within the same timestep.
Base class for regions, akin to Verilog regions for ordering events between threads within the same timestep. order is the order regions run in, with 0 being the default, and incrementing regions running later. TODO: have a more extensible ordering than ints.
- class StopException extends Exception
Indicates that a Chisel
stop()
statement was triggered. - class TemporalParadox extends Exception
- class TestResult extends AnyRef
- class ThreadOrderDependentException extends Exception
- class TimeoutException extends Exception
- class UnpokeableException extends Exception
- class UnsupportedOperationException extends Exception
- class ValidDriver[T <: Data] extends AnyRef
- type WriteLxtAnnotation = chiseltest.simulator.WriteLxtAnnotation
- implicit class testableBool extends AnyRef
allows access to chisel Bool type signals with Scala native values
- implicit class testableClock extends AnyRef
- implicit class testableData[T <: Data] extends AnyRef
- implicit class testableFixedPoint extends AnyRef
allows access to chisel FixedPoint type signals with Scala native values
- implicit class testableInterval extends AnyRef
allows access to chisel Interval type signals with Scala native values
- implicit class testableRecord[T <: Record] extends AnyRef
- implicit class testableSInt extends AnyRef
allows access to chisel SInt type signals with Scala native values
- implicit class testableUInt extends AnyRef
allows access to chisel UInt type signals with Scala native values
- implicit class testableVec[T <: Vec[_]] extends AnyRef
Value Members
- val IcarusBackendAnnotation: chiseltest.simulator.IcarusBackendAnnotation.type
- val TreadleBackendAnnotation: chiseltest.simulator.TreadleBackendAnnotation.type
- val VcsBackendAnnotation: chiseltest.simulator.VcsBackendAnnotation.type
- val VerilatorBackendAnnotation: chiseltest.simulator.VerilatorBackendAnnotation.type
- val WriteFsdbAnnotation: chiseltest.simulator.WriteFsdbAnnotation.type
- val WriteFstAnnotation: chiseltest.simulator.WriteFstAnnotation.type
- val WriteLxtAnnotation: chiseltest.simulator.WriteLxtAnnotation.type
- val WriteVcdAnnotation: chiseltest.simulator.WriteVcdAnnotation.type
- val WriteVpdAnnotation: chiseltest.simulator.WriteVpdAnnotation.type
- implicit def decoupledToDriver[T <: Data](x: ReadyValidIO[T]): DecoupledDriver[T]
- def parallel(run1: => Unit, run2: => Unit): Unit
- def timescope(contents: => Unit): Unit
- implicit def validToDriver[T <: Data](x: ValidIO[T]): ValidDriver[T]
- object ClockResolutionUtils
Provides clock-resolution-specific abstractions on top of getVar/setVar.
Provides clock-resolution-specific abstractions on top of getVar/setVar. For library builders, not top-level test writers.
- object DecoupledDriver
- object Monitor extends Region
- object RawTester
This is a simple tester that does not require that it be within the scope of a scalatest in order to run.
This is a simple tester that does not require that it be within the scope of a scalatest in order to run. This form is suitable for running in the Jupyter notebook.
- object Region
- object TestInstance
- object TestdriverMain extends Region
- object ValidDriver
- object fork extends ForkBuilder