RawStringParam
ir
RefNotInitializedException
CheckInitialization
Reference
ir
RegKind
firrtl
RegReqClk
CheckTypes
Rem
PrimOps
RemoveAccesses
passes
RemoveAllButClocks
clocklist
RemoveCHIRRTL
passes
RemoveEmpty
passes
RemoveReset
transforms
RemoveValidIf
passes
RenameAnnotatedMemoryPorts
memlib
RenameMap
firrtl
ReplSeqMem
memlib
ReplSeqMemAnnotation
memlib
ReplaceAccesses
passes
ReplaceMemMacros
memlib
ReqClk
CheckTypes
ResolveAndCheck
firrtl
ResolveGenders
passes
ResolveKinds
passes
ResolveMaskGranularity
memlib
ResolveMemoryReference
memlib
rdwrite
DataRef
reachableFrom
DiGraph
read
AnnotationYamlFormat
readLatency
DefMemory
DefAnnotatedMemory
readUnderWrite
DefMemory
DefAnnotatedMemory
readers
DefMemory
MPorts
DefAnnotatedMemory
readwriters
DefMemory
MPorts
DefAnnotatedMemory
realWidth
VRandom
remove_chirrtl_m
RemoveCHIRRTL
remove_chirrtl_s
RemoveCHIRRTL
remove_root
VerilogEmitter
rename
RenameMap
renameExps
LowerTypes
renameMap
RenameMap
renames
CircuitState
replaceExp
InferReadWritePass
VerilogMemDelays
replaceStmt
InferReadWritePass
VerilogMemDelays
reset
DefRegister
Logger
reset_block
FIRRTLParser
resolve_e
ResolveGenders
resolve_expr
ResolveKinds
resolve_gender
ResolveGenders
resolve_kinds
ResolveKinds
resolve_s
ResolveGenders
resolve_stmt
ResolveKinds
resourceId
BlackBoxResource
ret
Stop
reverse
DiGraph
run
CInferMDir
CInferTypes
CheckChirrtl
CheckGenders
CheckHighForm
CheckInitialization
CheckTypes
CheckWidths
CommonSubexpressionElimination
ConvertFixedToSInt
ExpandConnects
ExpandWhens
InferTypes
InferWidths
InlineInstances
Legalize
PadWidths
Pass
PullMuxes
RemoveAccesses
RemoveEmpty
RemoveValidIf
ReplaceAccesses
ResolveGenders
ResolveKinds
SplitExpressions
ToWorkingIR
VerilogModulusCleanup
VerilogPrep
VerilogRename
VerilogWrap
ClockList
RemoveAllButClocks
InferReadWritePass
RenameAnnotatedMemoryPorts
ResolveMaskGranularity
ResolveMemoryReference
ToMemIR
VerilogMemDelays
Wiring
DeadCodeElimination
DedupModules
runTransform
Transform
runTransforms
SeqTransformBased
ruw
FIRRTLParser