class SeparateWriteClocks extends Transform with DependencyAPIMigration
This transform introduces an intermediate wire on the clock field of each write port of synchronous-read memories that have *multiple* write/readwrite ports and undefined read-under-write collision behavior. Ultimately, the introduction of these intermediate wires does not change which clock net clocks each port; therefore, the purpose of this transform is to help generate Verilog that is more amenable to inference of RAM macros with multiple write ports in FPGA synthesis flows. This change will cause each write and each readwrite port to be emitted in a separate clocked procedure, yielding multiple benefits:
1) Separate write procedures avoid implicitly constraining cross-port read-write and write-write collision behaviors 2) The preference for separate clocked procedures for each write port is explicitly specified by Intel and Xilinx
While this feature is not intended to be vendor-specific, inference of *multiple-write* RAM macros from behavioral Verilog or VHDL requires both advanced underlying RAM primitives and advanced synthesis tools. Currently, mapping such memories to programmable devices beyond modern Intel and Xilinx architectures can be prohibitive for users.
Though the emission of separate processes for write ports could be absorbed into the Verilog emitter, the use of a pure-FIRRTL transform reduces implementation complexity and enhances reliability.
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def
execute(state: CircuitState): CircuitState
Perform the transform, encode renaming with RenameMap, and can delete annotations Called by runTransform.
Perform the transform, encode renaming with RenameMap, and can delete annotations Called by runTransform.
- state
Input Firrtl AST
- returns
A transformed Firrtl AST
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- SeparateWriteClocks → Transform
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final
def
getClass(): Class[_]
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getLogger: Logger
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hashCode(): Int
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def
invalidates(a: Transform): Boolean
A function that, given *another* transform (parameter
a
) will return true if this transform invalidates/undos the effects of the *other* transform (parametera
).A function that, given *another* transform (parameter
a
) will return true if this transform invalidates/undos the effects of the *other* transform (parametera
).- a
transform
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- SeparateWriteClocks → DependencyAPIMigration → Transform → DependencyAPI
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val
logger: Logger
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def
name: String
A convenience function useful for debugging and error messages
A convenience function useful for debugging and error messages
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def
ne(arg0: AnyRef): Boolean
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def
notify(): Unit
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def
notifyAll(): Unit
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def
optionalPrerequisiteOf: Seq[Dependency[SetDefaultReadUnderWrite]]
A sequence of transforms to add this transform as an
optionalPrerequisite
.A sequence of transforms to add this transform as an
optionalPrerequisite
. The use ofoptionalPrerequisiteOf
enables the transform declaring them to always run before some other transforms. However, declaringoptionalPrerequisiteOf
will not result in the sequence of transforms executing.This is useful for providing an ordering constraint to guarantee that other transforms (e.g., emitters) will not be scheduled before you.
- Definition Classes
- SeparateWriteClocks → DependencyAPIMigration → Transform → DependencyAPI
- Note
This method **will not** result in the listed transforms running. If you want to add multiple transforms at once, you should use a
DependencyManager
with multiple targets.
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def
optionalPrerequisites: Seq[Dependency[InferReadWrite]]
All transforms that, if a prerequisite of *another* transform, will run before this transform.
All transforms that, if a prerequisite of *another* transform, will run before this transform.
- Definition Classes
- SeparateWriteClocks → DependencyAPIMigration → Transform → DependencyAPI
- Note
The use of a Seq here is to preserve input order. Internally, this will be converted to a private, ordered Set.
-
def
prerequisites: Seq[Dependency[Transform with DependencyAPIMigration]]
All transform that must run before this transform
All transform that must run before this transform
- Definition Classes
- SeparateWriteClocks → DependencyAPIMigration → Transform → DependencyAPI
- Note
The use of a Seq here is to preserve input order. Internally, this will be converted to a private, ordered Set.
-
final
def
runTransform(state: CircuitState): CircuitState
Perform the transform and update annotations.
Perform the transform and update annotations.
- state
Input Firrtl AST
- returns
A transformed Firrtl AST
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synchronized[T0](arg0: ⇒ T0): T0
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toString(): String
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def
transform(state: CircuitState): CircuitState
A mathematical transform on some type
A mathematical transform on some type
- returns
an output object of the same type
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- Transform → TransformLike
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final
def
wait(arg0: Long, arg1: Int): Unit
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final
def
wait(arg0: Long): Unit
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final
def
wait(): Unit
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Deprecated Value Members
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def
dependents: Seq[Dependency[Transform]]
All transforms that must run after this transform
All transforms that must run after this transform
This is a means of prerequisite injection into some other transform. Normally a transform will define its own prerequisites. Dependents exist for two main situations:
First, they improve the composition of optional transforms. If some first transform is optional (e.g., an expensive validation check), you would like to be able to conditionally cause it to run. If it is listed as a prerequisite on some other, second transform then it must always run before that second transform. There's no way to turn it off. However, by listing the second transform as a dependent of the first transform, the first transform will only run (and be treated as a prerequisite of the second transform) if included in a list of target transforms that should be run.
Second, an external library would like to inject some first transform before a second transform inside FIRRTL. In this situation, the second transform cannot have any knowledge of external libraries. The use of a dependent here allows for prerequisite injection into FIRRTL proper.
- Definition Classes
- DependencyAPI
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- @deprecated
- Deprecated
(Since version FIRRTL 1.3) Due to confusion, 'dependents' is being renamed to 'optionalPrerequisiteOf'. Override the latter instead.
- Note
The use of a Seq here is to preserve input order. Internally, this will be converted to a private, ordered Set.
- See also
firrtl.passes.CheckTypes for an example of an optional checking firrtl.Transform
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def
finalize(): Unit
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final
def
inputForm: CircuitForm
- Definition Classes
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- @deprecated
- Deprecated
(Since version FIRRTL 1.3) Use Dependency API methods for equivalent functionality. See: https://bit.ly/2Voppre
-
final
def
outputForm: CircuitForm
- Definition Classes
- DependencyAPIMigration
- Annotations
- @deprecated
- Deprecated
(Since version FIRRTL 1.3) Use Dependency API methods for equivalent functionality. See: https://bit.ly/2Voppre
This is the documentation for Firrtl.