Packages

p

firrtl

passes

package passes

Ordering
  1. Alphabetic
Visibility
  1. Public
  2. All

Type Members

  1. trait CheckHighFormLike extends AnyRef
  2. case class DataRef(exp: Expression, source: String, sink: String, mask: String, rdwrite: Boolean) extends Product with Serializable
  3. class Errors extends AnyRef
  4. class ExpandWhensAndCheck extends Transform with DependencyAPIMigration
  5. class InferBinaryPoints extends Pass
  6. class InferWidths extends Transform with ResolvedAnnotationPaths with DependencyAPIMigration

    Infers the widths of all signals with unknown widths

    Infers the widths of all signals with unknown widths

    Is a global width inference algorithm - Instances of the same module with unknown input port widths will be assigned the largest width of all assignments to each of its instance ports - If you don't want the global inference behavior, then be sure to define all your input widths

    Infers the smallest width is larger than all assigned widths to a signal - Note that this means that dummy assignments that are overwritten by last-connect-semantics can still influence width inference - E.g. wire x: UInt x <= UInt<5>(15) x <= UInt<1>(1)

    Since width inference occurs before lowering, it infers x's width to be 5 but with an assignment of UInt(1):

    wire x: UInt<5> x <= UInt<1>(1)

    Uses firrtl.constraint package to infer widths

  7. case class InlineAnnotation(target: Named) extends SingleTargetAnnotation[Named] with Product with Serializable

    Indicates that something should be inlined

  8. class InlineInstances extends Transform with DependencyAPIMigration with RegisteredTransform

    Inline instances as indicated by existing InlineAnnotations

    Inline instances as indicated by existing InlineAnnotations

    Note

    Only use on legal Firrtl. Specifically, the restriction of instance loops must have been checked, or else this pass can infinitely recurse.

  9. case class MPort(name: String, clk: Expression) extends Product with Serializable
  10. case class MPorts(readers: ArrayBuffer[MPort], writers: ArrayBuffer[MPort], readwriters: ArrayBuffer[MPort]) extends Product with Serializable
  11. trait Pass extends Transform with DependencyAPIMigration

    Pass is simple transform that is generally part of a larger Transform Has an UnknownForm, because larger Transform should specify form

  12. class PassException extends FirrtlUserException
  13. class PassExceptions extends FirrtlUserException
  14. class RemoveIntervals extends Pass

    Replaces IntervalType with SIntType, three AST walks: 1) Align binary points

    Replaces IntervalType with SIntType, three AST walks: 1) Align binary points

    • adds shift operators to primop args and connections
    • does not affect declaration- or inferred-types 2) Replace Interval DefNode with DefWire + Connect
    • You have to do this to capture the smaller bitwidths of nodes that intervals give you. Otherwise, any future InferTypes would re-infer the larger widths on these nodes from SInt width inference rules 3) Replace declaration IntervalType's with SIntType's
    • for each declaration:
      1. remove non-zero binary points b. remove open bounds c. replace with SIntType 3) Run InferTypes
  15. class TrimIntervals extends Pass

    Replaces IntervalType with SIntType, three AST walks: 1) Align binary points

    Replaces IntervalType with SIntType, three AST walks: 1) Align binary points

    • adds shift operators to primop args and connections
    • does not affect declaration- or inferred-types 2) Replace declaration IntervalType's with SIntType's
    • for each declaration:
      1. remove non-zero binary points b. remove open bounds c. replace with SIntType 3) Run InferTypes
  16. case class WidthGeqConstraintAnnotation(loc: ReferenceTarget, exp: ReferenceTarget) extends Annotation with Product with Serializable
  17. class WrapWithRemainder extends PassException

Value Members

  1. object CInferMDir extends Pass
  2. object CInferTypes extends Pass
  3. object CheckChirrtl extends Pass with CheckHighFormLike
  4. object CheckFlows extends Pass
  5. object CheckHighForm extends Pass with CheckHighFormLike
  6. object CheckInitialization extends Pass

    Reports errors for any references that are not fully initialized

    Reports errors for any references that are not fully initialized

    Note

    This pass looks for firrtl.WVoids left behind by ExpandWhens

    ,

    Assumes single connection (ie. no last connect semantics)

  7. object CheckTypes extends Pass
  8. object CheckWidths extends Pass
  9. object CommonSubexpressionElimination extends Transform with HasShellOptions with DependencyAPIMigration
  10. object ConvertFixedToSInt extends Pass

    Replaces FixedType with SIntType, and correctly aligns all binary points

  11. object ExpandConnects extends Pass
  12. object ExpandWhens extends Pass

    Expand Whens

    Expand Whens

    This pass does the following things: $ - Remove last connect semantics $ - Remove conditional blocks $ - Eliminate concept of scoping $ - Consolidate attaches

    Note

    Assumes bulk connects and isInvalids have been expanded

    ,

    Assumes all references are declared

  13. object InferTypes extends Pass
  14. object InferWidths
  15. object InlineInstances
  16. object LegalizeConnects extends Pass

    Ensures that all connects + register inits have the same bit-width on the rhs and the lhs.

    Ensures that all connects + register inits have the same bit-width on the rhs and the lhs. The rhs is padded or bit-extacted to fit the width of the lhs.

    Note

    technically, width(rhs) > width(lhs) is not legal firrtl, however, we do not error for historic reasons.

  17. object LowerTypes extends Transform with DependencyAPIMigration

    Flattens Bundles and Vecs.

    Flattens Bundles and Vecs. - Some implicit bundle types remain, but with a limited depth:

    • the type of a memory is still a bundle with depth 2 (mem -> port -> field), see MemPortUtils.memType
    • the type of a module instance is still a bundle with depth 1 (instance -> port)
  18. object MemPortUtils
  19. object NoCommonSubexpressionEliminationAnnotation extends NoTargetAnnotation with Product with Serializable

    Indicate that CommonSubexpressionElimination should not be run

  20. object PadWidths extends Pass
  21. object PullMuxes extends Pass
  22. object RemoveAccesses extends Pass

    Removes all firrtl.WSubAccess from circuit

  23. object RemoveCHIRRTL extends Transform with DependencyAPIMigration
  24. object RemoveEmpty extends Pass with DependencyAPIMigration
  25. object RemoveValidIf extends Pass

    Remove ValidIf and replace IsInvalid with a connection to zero

  26. object ReplaceAccesses extends Pass

    Replaces constant firrtl.WSubAccess with firrtl.WSubIndex TODO Fold in to High Firrtl Const Prop

  27. object ResolveFlows extends Pass
  28. object ResolveKinds extends Pass
  29. object SplitExpressions extends Pass
  30. object VerilogModulusCleanup extends Pass

    Verilog has the width of (a % b) = Max(W(a), W(b)) FIRRTL has the width of (a % b) = Min(W(a), W(b)), which makes more sense, but nevertheless is a problem when emitting verilog

    Verilog has the width of (a % b) = Max(W(a), W(b)) FIRRTL has the width of (a % b) = Min(W(a), W(b)), which makes more sense, but nevertheless is a problem when emitting verilog

    This pass finds every instance of (a % b) and: 1) adds a temporary node equal to (a % b) with width Max(W(a), W(b)) 2) replaces the reference to (a % b) with a bitslice of the temporary node to get back down to width Min(W(a), W(b))

    This is technically incorrect firrtl, but allows the verilog emitter to emit correct verilog without needing to add temporary nodes

  31. object VerilogPrep extends Pass

    Makes changes to the Firrtl AST to make Verilog emission easier

    Makes changes to the Firrtl AST to make Verilog emission easier

    - For each instance, adds wires to connect to each port

    • Note that no Namespace is required because Uniquify ensures that there will be no collisions with the lowered names of instance ports - Also removes Attaches where a single Port OR Wire connects to 1 or more instance ports
    • These are expressed in the portCons of WDefInstConnectors
    Note

    The result of this pass is NOT legal Firrtl

  32. object ZeroLengthVecs extends Pass

    Handles dynamic accesses to zero-length vectors.

    Handles dynamic accesses to zero-length vectors.

    Note

    Removes assignments that use a zero-length vector as a sink

    ,

    Removes signals resulting from accesses to a zero-length vector from attach groups

    ,

    Removes attaches that become degenerate after zero-length-accessor removal

    ,

    Replaces "source" references to elements of zero-length vectors with always-invalid validif

  33. object ZeroWidth extends Transform with DependencyAPIMigration
  34. object createMask
  35. object toBitMask

    Given a mask, return a bitmask corresponding to the desired datatype.

    Given a mask, return a bitmask corresponding to the desired datatype. Requirements:

    • The mask type and datatype must be equivalent, except any ground type in datatype must be matched by a 1-bit wide UIntType.
    • The mask must be a reference, subfield, or subindex The bitmask is a series of concatenations of the single mask bit over the length of the corresponding ground type, e.g.:
    wire mask: {x: UInt<1>, y: UInt<1>}
wire data: {x: UInt<2>, y: SInt<2>}
// this would return:
cat(cat(mask.x, mask.x), cat(mask.y, mask.y))

Deprecated Value Members

  1. object ToWorkingIR extends Pass
    Annotations
    @deprecated
    Deprecated

    (Since version FIRRTL 1.4.2) This pass is an identity transform. For an equivalent dependency, use firrtl.stage.forms.MinimalHighForm

  2. object Uniquify extends Transform with DependencyAPIMigration

    Resolve name collisions that would occur in the old LowerTypes pass

    Resolve name collisions that would occur in the old LowerTypes pass

    Annotations
    @deprecated
    Deprecated

    (Since version FIRRTL 1.4.0) Uniquify is now part of LowerTypes

    Example: 

    1. wire a = { b, c }[2]
wire a_0

      This lowers to:

      wire a__0_b
wire a__0_c
wire a__1_b
wire a__1_c
wire a_0

      There wouldn't be a collision even if we didn't map a -> a_, but there WOULD be collisions in references a[0] and a_0 so we still have to rename a

    Note

    Must be run after InferTypes because ir.DefNodes need type

Ungrouped