Type Members

1.  case class Config(pin: Pin, source: Source, top: Top) extends Product with Serializable
2.  class CreateMemoryAnnotations extends Transform with DependencyAPIMigration
3.  case class DefAnnotatedMemory(info: Info, name: String, dataType: Type, depth: BigInt, writeLatency: Int, readLatency: Int, readers: Seq[String], writers: Seq[String], readwriters: Seq[String], readUnderWrite: ir.ReadUnderWrite.Value, maskGran: Option[BigInt], memRef: Option[(String, String)]) extends Statement with IsDeclaration with Product with Serializable
4.  sealed trait DefaultReadUnderWriteAnnotation extends NoTargetAnnotation
5.  class DumpMemoryAnnotations extends Transform with DependencyAPIMigration
6.  case class GenVerilogMemBehaviorModelAnno(genBlackBox: Boolean) extends NoTargetAnnotation with Product with Serializable
7.  class InferReadWrite extends Transform with DependencyAPIMigration with SeqTransformBased with HasShellOptions
8.  case class MemConf(name: String, depth: BigInt, width: Int, ports: Map[MemPort, Int], maskGranularity: Option[Int]) extends Product with Serializable
9.  class MemDelayAndReadwriteTransformer extends AnyRef

   This class performs the primary work of the transform: splitting readwrite ports into separate read and write ports while simultaneously compiling memory latencies to combinational-read memories with delay pipelines.

   This class performs the primary work of the transform: splitting readwrite ports into separate read and write ports while simultaneously compiling memory latencies to combinational-read memories with delay pipelines. It is represented as a class that takes a module as a constructor argument, as it encapsulates the mutable state required to analyze and transform one module.

   Note

   The final transformed module is found in the (sole public) field transformed

10.  class MemLibOptions extends RegisteredLibrary
11.  case class MemLibOutConfigFileAnnotation(file: String, annotatedMemories: Seq[DefAnnotatedMemory]) extends NoTargetAnnotation with CustomFileEmission with Product with Serializable

    Generate conf file for a sequence of DefAnnotatedMemory

    Generate conf file for a sequence of DefAnnotatedMemory

    Note

    file already has its suffix adding by --replSeqMem

12.  sealed abstract class MemPort extends AnyRef
13.  case class NoDedupMemAnnotation(target: ComponentName) extends SingleTargetAnnotation[ComponentName] with Product with Serializable

    A component, e.g.

    A component, e.g. register etc. Must be declared only once under the TopAnnotation

14.  sealed trait PassOption extends AnyRef
15.  case class Pin(name: String) extends Product with Serializable
16.  case class PinAnnotation(pins: Seq[String]) extends NoTargetAnnotation with Product with Serializable

    Annotates the name of the pins to add for WiringTransform

17.  class ReplSeqMem extends SeqTransform with HasShellOptions with DependencyAPIMigration
18.  case class ReplSeqMemAnnotation(inputFileName: String, outputConfig: String) extends NoTargetAnnotation with Product with Serializable
19.  class ReplaceMemMacros extends Transform with DependencyAPIMigration

    Replace DefAnnotatedMemory with memory blackbox + wrapper + conf file.

    Replace DefAnnotatedMemory with memory blackbox + wrapper + conf file. This will not generate wmask ports if not needed. Creates the minimum # of black boxes needed by the design.

20.  class ResolveMemoryReference extends Transform with DependencyAPIMigration

    Resolves annotation ref to memories that exactly match (except name) another memory

21.  class SeparateWriteClocks extends Transform with DependencyAPIMigration

    This transform introduces an intermediate wire on the clock field of each write port of synchronous-read memories that have *multiple* write/readwrite ports and undefined read-under-write collision behavior.

    This transform introduces an intermediate wire on the clock field of each write port of synchronous-read memories that have *multiple* write/readwrite ports and undefined read-under-write collision behavior. Ultimately, the introduction of these intermediate wires does not change which clock net clocks each port; therefore, the purpose of this transform is to help generate Verilog that is more amenable to inference of RAM macros with multiple write ports in FPGA synthesis flows. This change will cause each write and each readwrite port to be emitted in a separate clocked procedure, yielding multiple benefits:

    1) Separate write procedures avoid implicitly constraining cross-port read-write and write-write collision behaviors 2) The preference for separate clocked procedures for each write port is explicitly specified by Intel and Xilinx

    While this feature is not intended to be vendor-specific, inference of *multiple-write* RAM macros from behavioral Verilog or VHDL requires both advanced underlying RAM primitives and advanced synthesis tools. Currently, mapping such memories to programmable devices beyond modern Intel and Xilinx architectures can be prohibitive for users.

    Though the emission of separate processes for write ports could be absorbed into the Verilog emitter, the use of a pure-FIRRTL transform reduces implementation complexity and enhances reliability.

22.  class SetDefaultReadUnderWrite extends Transform with DependencyAPIMigration

    Adding a DefaultReadUnderWriteAnnotation and running the SetDefaultReadUnderWrite transform will cause all synchronous-read memories with 'undefined' read-under-write parameters to be assigned a default parameter value, either 'old' (read-first behavior) or 'new' (write-first behavior).

    Adding a DefaultReadUnderWriteAnnotation and running the SetDefaultReadUnderWrite transform will cause all synchronous-read memories with 'undefined' read-under-write parameters to be assigned a default parameter value, either 'old' (read-first behavior) or 'new' (write-first behavior). This can help generate Verilog that is amenable to RAM macro inference for various FPGA tools, or it can be used to satisfy other downstream design constraints.

23.  class SimpleMidTransform extends SimpleTransform
24.  case class Source(name: String, module: String) extends Product with Serializable
25.  case class Top(name: String) extends Product with Serializable
26.  class YamlFileReader extends AnyRef
27.  class YamlFileWriter extends AnyRef
28.  class SimpleTransform extends Transform

    Annotations

    @deprecated

    Deprecated

    (Since version FIRRTL 1.3) Migrate to a transform that does not take arguments. This will be removed in 1.4.