object Parser extends LazyLogging
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- def parse(text: String, infoMode: InfoMode): Circuit
- def parse(lines: Seq[String], infoMode: InfoMode): Circuit
- def parse(text: String): Circuit
Parse the concrete syntax of a FIRRTL firrtl.ir.Circuit, e.g.
Parse the concrete syntax of a FIRRTL firrtl.ir.Circuit, e.g.
"""circuit Top: | module Top: | input x: UInt | node y = x |""".stripMargin
becomes:
Circuit( NoInfo, Seq(Module( NoInfo, "Top", Seq(Port(NoInfo, "x", Input, UIntType(UnknownWidth))), Block(DefNode(NoInfo, "y", Ref("x", UnknownType))) )), "Top" )
- text
concrete Circuit syntax
- def parse(lines: Seq[String]): Circuit
- def parse(lines: Iterator[String], infoMode: InfoMode = UseInfo): Circuit
Takes Iterator over lines of FIRRTL, returns FirrtlNode (root node is Circuit)
- def parseCharStream(charStream: CharStream, infoMode: InfoMode): Circuit
Parses a org.antlr.v4.runtime.CharStream and returns a parsed Circuit
- def parseDefModule(module: String): DefModule
Parse the concrete syntax of a FIRRTL firrtl.ir.DefModule, e.g.
Parse the concrete syntax of a FIRRTL firrtl.ir.DefModule, e.g.
"""module Top: | input x: UInt | node y = x |""".stripMargin
becomes:
Module( NoInfo, "Top", Seq(Port(NoInfo, "x", Input, UIntType(UnknownWidth))), Block(DefNode(NoInfo, "y", Ref("x", UnknownType))) )
- module
concrete DefModule syntax
- def parseExpression(expr: String): Expression
Parse the concrete syntax of a FIRRTL firrtl.ir.Expression, e.g.
Parse the concrete syntax of a FIRRTL firrtl.ir.Expression, e.g. "add(x, y)" becomes:
DoPrim(Add, Seq(Ref("x", UnknownType), Ref("y", UnknownType), Nil, UnknownType)
- expr
concrete Expression syntax
- def parseFile(filename: String, infoMode: InfoMode): Circuit
Parses a file in a given filename and returns a parsed Circuit
- def parseInfo(info: String): Info
Parse the concrete syntax of a FIRRTL firrtl.ir.Info, e.g.
Parse the concrete syntax of a FIRRTL firrtl.ir.Info, e.g. "@[FPU.scala 509:25]" becomes:
FileInfo("FPU.scala 509:25")
- info
concrete Info syntax
- def parsePort(port: String): Port
Parse the concrete syntax of a FIRRTL firrtl.ir.Port, e.g.
Parse the concrete syntax of a FIRRTL firrtl.ir.Port, e.g. "input x: UInt" becomes:
Port(NoInfo, "x", Input, UIntType(UnknownWidth))
- port
concrete Port syntax
- def parseStatement(statement: String): Statement
Parse the concrete syntax of a FIRRTL firrtl.ir.Statement, e.g.
Parse the concrete syntax of a FIRRTL firrtl.ir.Statement, e.g. "wire x: UInt" becomes:
DefWire(NoInfo, "x", UIntType(UnknownWidth))
- statement
concrete Statement syntax
- def parseString(text: String, infoMode: InfoMode): Circuit
Parses a String and returns a parsed Circuit
- def parseType(tpe: String): Type
Parse the concrete syntax of a FIRRTL firrtl.ir.Type, e.g.
Parse the concrete syntax of a FIRRTL firrtl.ir.Type, e.g. "UInt<3>" becomes:
UIntType(IntWidth(BigInt(3)))
- tpe
concrete Type syntax
- final def synchronized[T0](arg0: => T0): T0
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- final def wait(arg0: Long, arg1: Int): Unit
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- case object IgnoreInfo extends InfoMode with Product with Serializable
- case object UseInfo extends InfoMode with Product with Serializable
This is the documentation for Firrtl.