abstract class Bundle extends Record
Base class for data types defined as a bundle of other data types.
Usage: extend this class (either as an anonymous or named class) and define members variables of Data subtypes to be elements in the Bundle.
Example of an anonymous IO bundle
class MyModule extends Module { val io = IO(new Bundle { val in = Input(UInt(64.W)) val out = Output(SInt(128.W)) }) }
Or as a named class
class Packet extends Bundle { val header = UInt(16.W) val addr = UInt(16.W) val data = UInt(32.W) } class MyModule extends Module { val inPacket = IO(Input(new Packet)) val outPacket = IO(Output(new Packet)) val reg = Reg(new Packet) reg := inPacket outPacket := reg }
The fields of a Bundle are stored in an ordered Map called "elements" in reverse order of definition
class MyBundle extends Bundle { val foo = UInt(8.W) val bar = UInt(8.W) } val wire = Wire(new MyBundle) wire.elements // VectorMap("bar" -> wire.bar, "foo" -> wire.foo)
- Source
- Aggregate.scala
- Grouped
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- Record
- Aggregate
- Data
- SourceInfoDoc
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- HasId
- InstanceId
- AnyRef
- Any
- by DataEquality
- by toConnectableDefault
- by ConnectableDefault
- by any2stringadd
- by StringFormat
- by Ensuring
- by ArrowAssoc
- Hide All
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- Public
- Protected
Instance Constructors
- new Bundle()(implicit compileOptions: CompileOptions)
Value Members
- final def !=(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- final def ##: Int
- Definition Classes
- AnyRef → Any
- def +(other: String): String
- def ->[B](y: B): (Bundle, B)
- final def :#=(producer: DontCare.type)(implicit sourceInfo: SourceInfo): Unit
The "mono-direction connection operator", aka the "coercion operator".
The "mono-direction connection operator", aka the "coercion operator".
For
consumer :#= producer
, all leaf members of consumer (regardless of relative flip) are driven by the corresponding leaf members of producer (regardless of relative flip)Identical to calling :<= and :>=, but swapping consumer/producer for :>= (order is irrelevant), e.g.: consumer :<= producer producer :>= consumer
Symbol reference:
- ':' is the consumer side
- '=' is the producer side
- '#' means to ignore flips, always drive from producer to consumer
The following restrictions apply:
- The Chisel type of consumer and producer must be the "same shape" recursively:
- All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
- All vector types are the same length
- All bundle types have the same member names, but the flips of members can be different between producer and consumer
- The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.
Additional notes: - Connecting two
util.DecoupledIO
's would connectbits
,valid
, ANDready
from producer to consumer (despiteready
being flipped) - Functionally equivalent to chisel3.:=, but different than Chisel.:=- producer
the right-hand-side of the connection, all members will be driving, none will be driven-to
- Implicit
- This member is added by an implicit conversion from Bundle toConnectableDefault[Bundle] performed by method ConnectableDefault in chisel3.Data.
- Definition Classes
- ConnectableOpExtension
- final def :#=[S <: Data](producer: connectable.Connectable[S])(implicit evidence: =:=[Bundle, S], sourceInfo: SourceInfo): Unit
The "mono-direction connection operator", aka the "coercion operator".
The "mono-direction connection operator", aka the "coercion operator".
For
consumer :#= producer
, all leaf members of consumer (regardless of relative flip) are driven by the corresponding leaf members of producer (regardless of relative flip)Identical to calling :<= and :>=, but swapping consumer/producer for :>= (order is irrelevant), e.g.: consumer :<= producer producer :>= consumer
Symbol reference:
- ':' is the consumer side
- '=' is the producer side
- '#' means to ignore flips, always drive from producer to consumer
The following restrictions apply:
- The Chisel type of consumer and producer must be the "same shape" recursively:
- All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
- All vector types are the same length
- All bundle types have the same member names, but the flips of members can be different between producer and consumer
- The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.
Additional notes: - Connecting two
util.DecoupledIO
's would connectbits
,valid
, ANDready
from producer to consumer (despiteready
being flipped) - Functionally equivalent to chisel3.:=, but different than Chisel.:=- producer
the right-hand-side of the connection, all members will be driving, none will be driven-to
- Implicit
- This member is added by an implicit conversion from Bundle toConnectableDefault[Bundle] performed by method ConnectableDefault in chisel3.Data.
- Definition Classes
- ConnectableOpExtension
- final def :#=[S <: Data](lProducer: => S)(implicit evidence: =:=[Bundle, S], sourceInfo: SourceInfo): Unit
The "mono-direction connection operator", aka the "coercion operator".
The "mono-direction connection operator", aka the "coercion operator".
For
consumer :#= producer
, all leaf members of consumer (regardless of relative flip) are driven by the corresponding leaf members of producer (regardless of relative flip)Identical to calling :<= and :>=, but swapping consumer/producer for :>= (order is irrelevant), e.g.: consumer :<= producer producer :>= consumer
Symbol reference:
- ':' is the consumer side
- '=' is the producer side
- '#' means to ignore flips, always drive from producer to consumer
The following restrictions apply:
- The Chisel type of consumer and producer must be the "same shape" recursively:
- All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
- All vector types are the same length
- All bundle types have the same member names, but the flips of members can be different between producer and consumer
- The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.
Additional notes: - Connecting two
util.DecoupledIO
's would connectbits
,valid
, ANDready
from producer to consumer (despiteready
being flipped) - Functionally equivalent to chisel3.:=, but different than Chisel.:=- Implicit
- This member is added by an implicit conversion from Bundle toConnectableDefault[Bundle] performed by method ConnectableDefault in chisel3.Data.
- Definition Classes
- ConnectableOpExtension
- final def :<=(producer: DontCare.type)(implicit sourceInfo: SourceInfo): Unit
The "aligned connection operator" between a producer and consumer.
The "aligned connection operator" between a producer and consumer.
For
consumer :<= producer
, each ofconsumer
's leaf members which are aligned with respect toconsumer
are driven from the correspondingproducer
leaf member. Onlyconsumer
's leaf/branch alignments influence the connection.Symbol reference:
- ':' is the consumer side
- '=' is the producer side
- '<' means to connect from producer to consumer
The following restrictions apply:
- The Chisel type of consumer and producer must be the "same shape" recursively:
- All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
- All vector types are the same length
- All bundle types have the same member names, but the flips of members can be different between producer and consumer
- The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.
Additional notes:
- Connecting two
util.DecoupledIO
's would connectbits
andvalid
from producer to consumer, but leaveready
unconnected
- producer
the right-hand-side of the connection; will always drive leaf connections, and never get driven by leaf connections ("aligned connection")
- Implicit
- This member is added by an implicit conversion from Bundle toConnectableDefault[Bundle] performed by method ConnectableDefault in chisel3.Data.
- Definition Classes
- ConnectableOpExtension
- final def :<=[S <: Data](producer: connectable.Connectable[S])(implicit evidence: =:=[Bundle, S], sourceInfo: SourceInfo): Unit
The "aligned connection operator" between a producer and consumer.
The "aligned connection operator" between a producer and consumer.
For
consumer :<= producer
, each ofconsumer
's leaf members which are aligned with respect toconsumer
are driven from the correspondingproducer
leaf member. Onlyconsumer
's leaf/branch alignments influence the connection.Symbol reference:
- ':' is the consumer side
- '=' is the producer side
- '<' means to connect from producer to consumer
The following restrictions apply:
- The Chisel type of consumer and producer must be the "same shape" recursively:
- All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
- All vector types are the same length
- All bundle types have the same member names, but the flips of members can be different between producer and consumer
- The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.
Additional notes:
- Connecting two
util.DecoupledIO
's would connectbits
andvalid
from producer to consumer, but leaveready
unconnected
- producer
the right-hand-side of the connection; will always drive leaf connections, and never get driven by leaf connections ("aligned connection")
- Implicit
- This member is added by an implicit conversion from Bundle toConnectableDefault[Bundle] performed by method ConnectableDefault in chisel3.Data.
- Definition Classes
- ConnectableOpExtension
- final def :<=[S <: Data](lProducer: => S)(implicit evidence: =:=[Bundle, S], sourceInfo: SourceInfo): Unit
The "aligned connection operator" between a producer and consumer.
The "aligned connection operator" between a producer and consumer.
For
consumer :<= producer
, each ofconsumer
's leaf members which are aligned with respect toconsumer
are driven from the correspondingproducer
leaf member. Onlyconsumer
's leaf/branch alignments influence the connection.Symbol reference:
- ':' is the consumer side
- '=' is the producer side
- '<' means to connect from producer to consumer
The following restrictions apply:
- The Chisel type of consumer and producer must be the "same shape" recursively:
- All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
- All vector types are the same length
- All bundle types have the same member names, but the flips of members can be different between producer and consumer
- The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.
Additional notes:
- Connecting two
util.DecoupledIO
's would connectbits
andvalid
from producer to consumer, but leaveready
unconnected
- Implicit
- This member is added by an implicit conversion from Bundle toConnectableDefault[Bundle] performed by method ConnectableDefault in chisel3.Data.
- Definition Classes
- ConnectableOpExtension
- final def :<>=(producer: DontCare.type)(implicit sourceInfo: SourceInfo): Unit
The "bi-direction connection operator", aka the "tur-duck-en operator"
The "bi-direction connection operator", aka the "tur-duck-en operator"
For
consumer :<>= producer
, both producer and consumer leafs could be driving or be driven-to. Theconsumer
's members aligned w.r.t.consumer
will be driven by corresponding members ofproducer
; theproducer
's members flipped w.r.t.producer
will be driven by corresponding members ofconsumer
Identical to calling
:<=
and:>=
in sequence (order is irrelevant), e.g.consumer :<= producer
thenconsumer :>= producer
Symbol reference:
- ':' is the consumer side
- '=' is the producer side
- '<' means to connect from producer to consumer
- '>' means to connect from consumer to producer
The following restrictions apply:
- The Chisel type of consumer and producer must be the "same shape" recursively:
- All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
- All vector types are the same length
- All bundle types have the same member names, but the flips of members can be different between producer and consumer
- The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.
- An additional type restriction is that all relative orientations of
consumer
andproducer
must match exactly.
Additional notes:
- Connecting two wires of
util.DecoupledIO
chisel type would connectbits
andvalid
from producer to consumer, andready
from consumer to producer. - If the types of consumer and producer also have identical relative flips, then we can emit FIRRTL.<= as it is a stricter version of chisel3.:<>=
- "turk-duck-en" is a dish where a turkey is stuffed with a duck, which is stuffed with a chicken;
:<>=
is a:=
stuffed with a<>
- producer
the right-hand-side of the connection
- Implicit
- This member is added by an implicit conversion from Bundle toConnectableDefault[Bundle] performed by method ConnectableDefault in chisel3.Data.
- Definition Classes
- ConnectableOpExtension
- final def :<>=[S <: Data](producer: connectable.Connectable[S])(implicit evidence: =:=[Bundle, S], sourceInfo: SourceInfo): Unit
The "bi-direction connection operator", aka the "tur-duck-en operator"
The "bi-direction connection operator", aka the "tur-duck-en operator"
For
consumer :<>= producer
, both producer and consumer leafs could be driving or be driven-to. Theconsumer
's members aligned w.r.t.consumer
will be driven by corresponding members ofproducer
; theproducer
's members flipped w.r.t.producer
will be driven by corresponding members ofconsumer
Identical to calling
:<=
and:>=
in sequence (order is irrelevant), e.g.consumer :<= producer
thenconsumer :>= producer
Symbol reference:
- ':' is the consumer side
- '=' is the producer side
- '<' means to connect from producer to consumer
- '>' means to connect from consumer to producer
The following restrictions apply:
- The Chisel type of consumer and producer must be the "same shape" recursively:
- All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
- All vector types are the same length
- All bundle types have the same member names, but the flips of members can be different between producer and consumer
- The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.
- An additional type restriction is that all relative orientations of
consumer
andproducer
must match exactly.
Additional notes:
- Connecting two wires of
util.DecoupledIO
chisel type would connectbits
andvalid
from producer to consumer, andready
from consumer to producer. - If the types of consumer and producer also have identical relative flips, then we can emit FIRRTL.<= as it is a stricter version of chisel3.:<>=
- "turk-duck-en" is a dish where a turkey is stuffed with a duck, which is stuffed with a chicken;
:<>=
is a:=
stuffed with a<>
- producer
the right-hand-side of the connection
- Implicit
- This member is added by an implicit conversion from Bundle toConnectableDefault[Bundle] performed by method ConnectableDefault in chisel3.Data.
- Definition Classes
- ConnectableOpExtension
- final def :<>=[S <: Data](lProducer: => S)(implicit evidence: =:=[Bundle, S], sourceInfo: SourceInfo): Unit
The "bi-direction connection operator", aka the "tur-duck-en operator"
The "bi-direction connection operator", aka the "tur-duck-en operator"
For
consumer :<>= producer
, both producer and consumer leafs could be driving or be driven-to. Theconsumer
's members aligned w.r.t.consumer
will be driven by corresponding members ofproducer
; theproducer
's members flipped w.r.t.producer
will be driven by corresponding members ofconsumer
Identical to calling
:<=
and:>=
in sequence (order is irrelevant), e.g.consumer :<= producer
thenconsumer :>= producer
Symbol reference:
- ':' is the consumer side
- '=' is the producer side
- '<' means to connect from producer to consumer
- '>' means to connect from consumer to producer
The following restrictions apply:
- The Chisel type of consumer and producer must be the "same shape" recursively:
- All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
- All vector types are the same length
- All bundle types have the same member names, but the flips of members can be different between producer and consumer
- The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.
- An additional type restriction is that all relative orientations of
consumer
andproducer
must match exactly.
Additional notes:
- Connecting two wires of
util.DecoupledIO
chisel type would connectbits
andvalid
from producer to consumer, andready
from consumer to producer. - If the types of consumer and producer also have identical relative flips, then we can emit FIRRTL.<= as it is a stricter version of chisel3.:<>=
- "turk-duck-en" is a dish where a turkey is stuffed with a duck, which is stuffed with a chicken;
:<>=
is a:=
stuffed with a<>
- Implicit
- This member is added by an implicit conversion from Bundle toConnectableDefault[Bundle] performed by method ConnectableDefault in chisel3.Data.
- Definition Classes
- ConnectableOpExtension
- final def :=(that: => Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit
The "strong connect" operator.
The "strong connect" operator.
For chisel3._, this operator is mono-directioned; all sub-elements of
this
will be driven by sub-elements ofthat
.- Equivalent to
this :#= that
For Chisel._, this operator connections bi-directionally via emitting the FIRRTL.<=
- Equivalent to
this :<>= that
- that
the Data to connect from
- Definition Classes
- Data
- Equivalent to
- final def :>=(producer: DontCare.type)(implicit sourceInfo: SourceInfo): Unit
The "flipped connection operator", or the "backpressure connection operator" between a producer and consumer.
The "flipped connection operator", or the "backpressure connection operator" between a producer and consumer.
For
consumer :>= producer
, each ofproducer
's leaf members which are flipped with respect toproducer
are driven from the corresponding consumer leaf member Onlyproducer
's leaf/branch alignments influence the connection.Symbol reference:
- ':' is the consumer side
- '=' is the producer side
- '>' means to connect from consumer to producer
The following restrictions apply:
- The Chisel type of consumer and producer must be the "same shape" recursively:
- All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
- All vector types are the same length
- All bundle types have the same member names, but the flips of members can be different between producer and consumer
- The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.
Additional notes:
- Connecting two
util.DecoupledIO
's would connectready
from consumer to producer, but leavebits
andvalid
unconnected
- producer
the right-hand-side of the connection; will always be driven by leaf connections, and never drive leaf connections ("flipped connection")
- Implicit
- This member is added by an implicit conversion from Bundle toConnectableDefault[Bundle] performed by method ConnectableDefault in chisel3.Data.
- Definition Classes
- ConnectableOpExtension
- final def :>=[S <: Data](producer: connectable.Connectable[S])(implicit evidence: =:=[Bundle, S], sourceInfo: SourceInfo): Unit
The "flipped connection operator", or the "backpressure connection operator" between a producer and consumer.
The "flipped connection operator", or the "backpressure connection operator" between a producer and consumer.
For
consumer :>= producer
, each ofproducer
's leaf members which are flipped with respect toproducer
are driven from the corresponding consumer leaf member Onlyproducer
's leaf/branch alignments influence the connection.Symbol reference:
- ':' is the consumer side
- '=' is the producer side
- '>' means to connect from consumer to producer
The following restrictions apply:
- The Chisel type of consumer and producer must be the "same shape" recursively:
- All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
- All vector types are the same length
- All bundle types have the same member names, but the flips of members can be different between producer and consumer
- The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.
Additional notes:
- Connecting two
util.DecoupledIO
's would connectready
from consumer to producer, but leavebits
andvalid
unconnected
- producer
the right-hand-side of the connection; will always be driven by leaf connections, and never drive leaf connections ("flipped connection")
- Implicit
- This member is added by an implicit conversion from Bundle toConnectableDefault[Bundle] performed by method ConnectableDefault in chisel3.Data.
- Definition Classes
- ConnectableOpExtension
- final def :>=[S <: Data](lProducer: => S)(implicit evidence: =:=[Bundle, S], sourceInfo: SourceInfo): Unit
The "flipped connection operator", or the "backpressure connection operator" between a producer and consumer.
The "flipped connection operator", or the "backpressure connection operator" between a producer and consumer.
For
consumer :>= producer
, each ofproducer
's leaf members which are flipped with respect toproducer
are driven from the corresponding consumer leaf member Onlyproducer
's leaf/branch alignments influence the connection.Symbol reference:
- ':' is the consumer side
- '=' is the producer side
- '>' means to connect from consumer to producer
The following restrictions apply:
- The Chisel type of consumer and producer must be the "same shape" recursively:
- All ground types are the same (UInt and UInt are same, SInt and UInt are not), but widths can be different (implicit trunction/padding occurs)
- All vector types are the same length
- All bundle types have the same member names, but the flips of members can be different between producer and consumer
- The leaf members that are ultimately assigned to, must be assignable. This means they cannot be module inputs or instance outputs.
Additional notes:
- Connecting two
util.DecoupledIO
's would connectready
from consumer to producer, but leavebits
andvalid
unconnected
- Implicit
- This member is added by an implicit conversion from Bundle toConnectableDefault[Bundle] performed by method ConnectableDefault in chisel3.Data.
- Definition Classes
- ConnectableOpExtension
- final def <>(that: => Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit
The "bulk connect operator", assigning elements in this Vec from elements in a Vec.
The "bulk connect operator", assigning elements in this Vec from elements in a Vec.
For chisel3._, uses the
chisel3.internal.BiConnect
algorithm; sub-elements of thatmay end up driving sub-elements of
this- Complicated semantics, hard to write quickly, will likely be deprecated in the future
For Chisel._, emits the FIRRTL.<- operator
- Equivalent to
this :<>= that
without the restrictions that bundle field names and vector sizes must match
- that
the Data to connect from
- Definition Classes
- Data
- final def ==(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- def ===(rhs: Bundle): Bool
Dynamic recursive equality operator for generic Data
Dynamic recursive equality operator for generic Data
- Implicit
- This member is added by an implicit conversion from Bundle toDataEquality[Bundle] performed by method DataEquality in chisel3.Data.
- Definition Classes
- DataEquality
- Exceptions thrown
ChiselException
whenlhs
andrhs
are different types during elaboration time
- def _cloneTypeImpl: Record
Implementation of cloneType that is [optionally for Record] overridden by the compiler plugin
Implementation of cloneType that is [optionally for Record] overridden by the compiler plugin
- Attributes
- protected
- Definition Classes
- Record
- Note
This should _never_ be overridden or called in user-code
- def _elementsImpl: Iterable[(String, Any)]
This method is implemented by the compiler plugin
This method is implemented by the compiler plugin
- Attributes
- protected
- Note
For some reason, the Scala compiler errors on child classes if this method is made virtual. It appears that the way the plugin implements this method is insufficient for implementing virtual methods. It is probably better kept concrete for future refactoring.
- def _usingPlugin: Boolean
Indicates if a concrete Bundle class was compiled using the compiler plugin
Indicates if a concrete Bundle class was compiled using the compiler plugin
Used for optimizing Chisel's performance and testing Chisel itself
- Attributes
- protected
- Note
This should not be used in user code!
- final def asInstanceOf[T0]: T0
- Definition Classes
- Any
- macro def asTypeOf[T <: Data](that: T): T
Does a reinterpret cast of the bits in this node into the format that provides.
Does a reinterpret cast of the bits in this node into the format that provides. Returns a new Wire of that type. Does not modify existing nodes.
x.asTypeOf(that) performs the inverse operation of x := that.toBits.
- Definition Classes
- Data
- Note
bit widths are NOT checked, may pad or drop bits from input
,that should have known widths
- final macro def asUInt: UInt
Reinterpret cast to UInt.
Reinterpret cast to UInt.
- Definition Classes
- Data
- Note
value not guaranteed to be preserved: for example, a SInt of width 3 and value -1 (0b111) would become an UInt with value 7
,Aggregates are recursively packed with the first element appearing in the least-significant bits of the result.
- def autoSeed(name: String): Bundle.this.type
Takes the last seed suggested.
Takes the last seed suggested. Multiple calls to this function will take the last given seed, unless this HasId is a module port (see overridden method in Data.scala).
If the final computed name conflicts with the final name of another signal, the final name may get uniquified by appending a digit at the end of the name.
Is a lower priority than suggestName, in that regardless of whether autoSeed was called, suggestName will always take precedence if it was called.
- returns
this object
- Definition Classes
- Data → HasId
- val base: Bundle
- Implicit
- This member is added by an implicit conversion from Bundle toConnectable[Bundle] performed by method toConnectableDefault in chisel3.Data.
- Definition Classes
- Connectable
- def binding: Option[Binding]
- def binding_=(target: Binding): Unit
- Attributes
- protected
- Definition Classes
- Data
- def circuitName: String
- Attributes
- protected
- Definition Classes
- HasId
- def className: String
Name for Pretty Printing
- def clone(): AnyRef
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.CloneNotSupportedException]) @native() @HotSpotIntrinsicCandidate()
- def cloneType: Bundle.this.type
Internal API; Chisel users should look at chisel3.chiselTypeOf(...).
- def do_asTypeOf[T <: Data](that: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T
- Definition Classes
- Data
- def do_asUInt(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt
- final lazy val elements: SeqMap[String, Data]
The collection of Data
The collection of Data
Elements defined earlier in the Bundle are higher order upon serialization. For example:
- Definition Classes
- Bundle → Record
class MyBundle extends Bundle { val foo = UInt(16.W) val bar = UInt(16.W) } // Note that foo is higher order because its defined earlier in the Bundle val bundle = Wire(new MyBundle) bundle.foo := 0x1234.U bundle.bar := 0x5678.U val uint = bundle.asUInt assert(uint === "h12345678".U) // This will pass
Example: - def ensuring(cond: (Bundle) => Boolean, msg: => Any): Bundle
- def ensuring(cond: (Bundle) => Boolean): Bundle
- def ensuring(cond: Boolean, msg: => Any): Bundle
- def ensuring(cond: Boolean): Bundle
- final def eq(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- def equals(that: Any): Boolean
- Definition Classes
- HasId → AnyRef → Any
- final def getClass(): Class[_ <: AnyRef]
- Definition Classes
- AnyRef → Any
- Annotations
- @native() @HotSpotIntrinsicCandidate()
- def getElements: Seq[Data]
Returns a Seq of the immediate contents of this Aggregate, in order.
- final def getWidth: Int
Returns the width, in bits, if currently known.
Returns the width, in bits, if currently known.
- Definition Classes
- Data
- def hasSeed: Boolean
- returns
Whether either autoName or suggestName has been called
- Definition Classes
- HasId
- def hashCode(): Int
- Definition Classes
- HasId → AnyRef → Any
- def ignoreSeq: Boolean
Overridden by IgnoreSeqInBundle to allow arbitrary Seqs of Chisel elements.
- def instanceName: String
- Definition Classes
- HasId → InstanceId
- final def isInstanceOf[T0]: Boolean
- Definition Classes
- Any
- def isLit: Boolean
- Definition Classes
- Data
- final def isWidthKnown: Boolean
Returns whether the width is currently known.
Returns whether the width is currently known.
- Definition Classes
- Data
- def litOption: Option[BigInt]
Return an Aggregate's literal value if it is a literal, None otherwise.
- def litValue: BigInt
Returns the literal value if this is a literal that is representable as bits, otherwise crashes.
Returns the literal value if this is a literal that is representable as bits, otherwise crashes.
- Definition Classes
- Data
- final def ne(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- def notSpecial: Boolean
True if no members are waived or squeezed
True if no members are waived or squeezed
- Implicit
- This member is added by an implicit conversion from Bundle toConnectable[Bundle] performed by method toConnectableDefault in chisel3.Data.
- Definition Classes
- Connectable
- final def notify(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @HotSpotIntrinsicCandidate()
- final def notifyAll(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @HotSpotIntrinsicCandidate()
- def parentModName: String
- Definition Classes
- HasId → InstanceId
- def parentPathName: String
- Definition Classes
- HasId → InstanceId
- def pathName: String
- Definition Classes
- HasId → InstanceId
- def squeeze(members: (Bundle) => Data*): connectable.Connectable[Bundle]
Select members of base to squeeze
Select members of base to squeeze
- members
functions given the base return a member to squeeze
- Implicit
- This member is added by an implicit conversion from Bundle toConnectable[Bundle] performed by method toConnectableDefault in chisel3.Data.
- Definition Classes
- Connectable
- def squeeze: connectable.Connectable[Bundle]
Adds base to squeezes
Adds base to squeezes
- Implicit
- This member is added by an implicit conversion from Bundle toConnectable[Bundle] performed by method toConnectableDefault in chisel3.Data.
- Definition Classes
- Connectable
- def squeezeAll: connectable.Connectable[Bundle]
Squeeze all members of base
Squeeze all members of base
- Implicit
- This member is added by an implicit conversion from Bundle toConnectable[Bundle] performed by method toConnectableDefault in chisel3.Data.
- Definition Classes
- Connectable
- def squeezeEach[S <: Data](pf: PartialFunction[Data, Seq[Data]]): connectable.Connectable[Bundle]
Programmatically select members of base to squeeze
Programmatically select members of base to squeeze
- Implicit
- This member is added by an implicit conversion from Bundle toConnectable[Bundle] performed by method toConnectableDefault in chisel3.Data.
- Definition Classes
- Connectable
- def suggestName(seed: => String): Bundle.this.type
Takes the first seed suggested.
Takes the first seed suggested. Multiple calls to this function will be ignored. If the final computed name conflicts with another name, it may get uniquified by appending a digit at the end.
Is a higher priority than
autoSeed
, in that regardless of whetherautoSeed
was called, suggestName will always take precedence.- seed
The seed for the name of this component
- returns
this object
- Definition Classes
- HasId
- final def synchronized[T0](arg0: => T0): T0
- Definition Classes
- AnyRef
- final def toAbsoluteTarget: ReferenceTarget
Returns a FIRRTL IsMember that refers to the absolute path to this object in the elaborated hardware graph
Returns a FIRRTL IsMember that refers to the absolute path to this object in the elaborated hardware graph
- Definition Classes
- NamedComponent → InstanceId
- final def toNamed: ComponentName
Returns a FIRRTL ComponentName that references this object
Returns a FIRRTL ComponentName that references this object
- Definition Classes
- NamedComponent → InstanceId
- Note
Should not be called until circuit elaboration is complete
- def toPrintable: Printable
Default "pretty-print" implementation Analogous to printing a Map Results in "
Bundle(elt0.name -> elt0.value, ...)
" - def toString(): String
The collection of chisel3.Data
The collection of chisel3.Data
This underlying datastructure is a ListMap because the elements must remain ordered for serialization/deserialization. Elements added later are higher order when serialized (this is similar to
Vec
). For example:// Assume we have some type MyRecord that creates a Record from the ListMap val record = MyRecord(ListMap("fizz" -> UInt(16.W), "buzz" -> UInt(16.W))) // "buzz" is higher order because it was added later than "fizz" record("fizz") := "hdead".U record("buzz") := "hbeef".U val uint = record.asUInt assert(uint === "hbeefdead".U) // This will pass
- Definition Classes
- Record → AnyRef → Any
- final def toTarget: ReferenceTarget
Returns a FIRRTL ReferenceTarget that references this object
Returns a FIRRTL ReferenceTarget that references this object
- Definition Classes
- NamedComponent → InstanceId
- Note
Should not be called until circuit elaboration is complete
- final def wait(arg0: Long, arg1: Int): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- final def wait(arg0: Long): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException]) @native()
- final def wait(): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- def waive(members: (Bundle) => Data*): connectable.Connectable[Bundle]
Select members of base to waive
Select members of base to waive
- members
functions given the base return a member to waive
- Implicit
- This member is added by an implicit conversion from Bundle toConnectable[Bundle] performed by method toConnectableDefault in chisel3.Data.
- Definition Classes
- Connectable
- def waiveAll: connectable.Connectable[Bundle]
Waive all members of base
Waive all members of base
- Implicit
- This member is added by an implicit conversion from Bundle toConnectable[Bundle] performed by method toConnectableDefault in chisel3.Data.
- Definition Classes
- Connectable
- def waiveAllAs[S <: Data](implicit ev: <:<[Bundle, S]): connectable.Connectable[S]
Waive all members of base and static cast to a new type
Waive all members of base and static cast to a new type
- Implicit
- This member is added by an implicit conversion from Bundle toConnectable[Bundle] performed by method toConnectableDefault in chisel3.Data.
- Definition Classes
- Connectable
- def waiveAs[S <: Data](members: (Bundle) => Data*)(implicit ev: <:<[Bundle, S]): connectable.Connectable[S]
Select members of base to waive and static cast to a new type
Select members of base to waive and static cast to a new type
- members
functions given the base return a member to waive
- Implicit
- This member is added by an implicit conversion from Bundle toConnectable[Bundle] performed by method toConnectableDefault in chisel3.Data.
- Definition Classes
- Connectable
- def waiveEach[S <: Data](pf: PartialFunction[Data, Seq[Data]])(implicit ev: <:<[Bundle, S]): connectable.Connectable[S]
Programmatically select members of base to waive and static cast to a new type
Programmatically select members of base to waive and static cast to a new type
- Implicit
- This member is added by an implicit conversion from Bundle toConnectable[Bundle] performed by method toConnectableDefault in chisel3.Data.
- Definition Classes
- Connectable
- final def widthOption: Option[Int]
Returns Some(width) if the width is known, else None.
Returns Some(width) if the width is known, else None.
- Definition Classes
- Data
Deprecated Value Members
- def finalize(): Unit
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.Throwable]) @Deprecated
- Deprecated
- def formatted(fmtstr: String): String
- Implicit
- This member is added by an implicit conversion from Bundle toStringFormat[Bundle] performed by method StringFormat in scala.Predef.
- Definition Classes
- StringFormat
- Annotations
- @deprecated @inline()
- Deprecated
(Since version 2.12.16) Use
formatString.format(value)
instead ofvalue.formatted(formatString)
, or use thef""
string interpolator. In Java 15 and later,formatted
resolves to the new method in String which has reversed parameters.
- def →[B](y: B): (Bundle, B)
- Implicit
- This member is added by an implicit conversion from Bundle toArrowAssoc[Bundle] performed by method ArrowAssoc in scala.Predef.
- Definition Classes
- ArrowAssoc
- Annotations
- @deprecated
- Deprecated
(Since version 2.13.0) Use
->
instead. If you still wish to display it as one character, consider using a font with programming ligatures such as Fira Code.
Inherited from Record
Inherited from Aggregate
Inherited from Data
Inherited from SourceInfoDoc
Inherited from NamedComponent
Inherited from HasId
Inherited from InstanceId
Inherited from AnyRef
Inherited from Any
Inherited by implicit conversion DataEquality fromBundle to DataEquality[Bundle]
Inherited by implicit conversion toConnectableDefault fromBundle to Connectable[Bundle]
Inherited by implicit conversion ConnectableDefault fromBundle to ConnectableDefault[Bundle]
connection
Ungrouped
SourceInfoTransformMacro
These internal methods are not part of the public-facing API!
The equivalent public-facing methods do not have the do_
prefix or have the same name. Use and look at the
documentation for those. If you want left shift, use <<
, not do_<<
. If you want conversion to a
Seq of Bools look at the asBools
above, not the one below. Users can safely ignore
every method in this group!
🐉🐉🐉 Here be dragons... 🐉🐉🐉
These do_X
methods are used to enable both implicit passing of SourceInfo and chisel3.CompileOptions
while also supporting chained apply methods. In effect all "normal" methods that you, as a user, will use in your
designs, are converted to their "hidden", do_*
, via macro transformations. Without using macros here, only one
of the above wanted behaviors is allowed (implicit passing and chained applies)---the compiler interprets a
chained apply as an explicit 'implicit' argument and will throw type errors.
The "normal", public-facing methods then take no SourceInfo. However, a macro transforms this public-facing method
into a call to an internal, hidden do_*
that takes an explicit SourceInfo by inserting an
implicitly[SourceInfo]
as the explicit argument.
This is the documentation for Chisel.
Package structure
The chisel3 package presents the public API of Chisel. It contains the concrete core types
UInt
,SInt
,Bool
,FixedPoint
,Clock
, andReg
, the abstract typesBits
,Aggregate
, andData
, and the aggregate typesBundle
andVec
.The Chisel package is a compatibility layer that attempts to provide chisel2 compatibility in chisel3.
Utility objects and methods are found in the
util
package.The
testers
package defines the basic interface for chisel testers.