dfhdl.compiler.stages
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This stage adds clock and reset ports across the entire design. For each design, clock and reset ports are added once per unique domain configuration.
This stage adds clock and reset ports across the entire design. For each design, clock and reset ports are added once per unique domain configuration.
Attributes
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- object
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class Objecttrait Matchableclass Any
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- Companion
- trait
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class Objecttrait Matchableclass Any
- Self type
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BackendCompiler.type
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class Objecttrait Matchableclass Any
- Self type
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CompiledDesign.type
This connects clock and reset ports across the entire design
This connects clock and reset ports across the entire design
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trait Singletontrait Producttrait Mirrorclass Stagetrait HasTypeNametrait Serializabletrait Producttrait Equalsclass Objecttrait Matchableclass AnyShow all
- Self type
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ConnectClkRst.type
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trait Singletontrait Producttrait Mirrorclass Stagetrait HasTypeNametrait Serializabletrait Producttrait Equalsclass Objecttrait Matchableclass AnyShow all
- Self type
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DFHDLUniqueNames.type
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trait Singletontrait Producttrait Mirrorclass Stagetrait HasTypeNametrait Serializabletrait Producttrait Equalsclass Objecttrait Matchableclass AnyShow all
- Self type
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trait Singletontrait Producttrait Mirrorclass DropLocalDclsclass Stagetrait HasTypeNametrait Serializabletrait Producttrait Equalsclass Objecttrait Matchableclass AnyShow all
- Self type
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DropCondDcls.type
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- Companion
- object
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class Stagetrait HasTypeNametrait Serializabletrait Producttrait Equalsclass Objecttrait Matchableclass AnyShow all
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object DropCondDcls.typeobject DropLocalDcls.type
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- class
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trait Singletontrait Producttrait Mirrorclass DropLocalDclsclass Stagetrait HasTypeNametrait Serializabletrait Producttrait Equalsclass Objecttrait Matchableclass AnyShow all
- Self type
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DropLocalDcls.type
This stage drops register aliases (e.g., x.reg
) and replaces them with explicit register variables. The most complex mechanism about this stage is the naming conversion convention.
This stage drops register aliases (e.g., x.reg
) and replaces them with explicit register variables. The most complex mechanism about this stage is the naming conversion convention.
- If
.reg
is applied on a named immutable valuex
or a mutated wire/port that is mutated only once, then that register variable will be namedx_reg
. If we have several register stages applied, then we create an enumeration. Sox.reg(2)
yieldsx_reg1
andx_reg2
. - If
.reg
is applied on a named mutable wirex
that is mutated more than once, then we treat every new.reg
application as a new version of x. In this case we get an enumeration of the version. E.g.:
val i = DFUInt(8) <> IN
val o = DFUInt(8) <> OUT
val x = DFUInt(8) <> WIRE
x := i
o := x.reg //x_ver1_reg
x := i + 1
o := x.reg(2) //x_ver2_reg1, x_ver2_reg2
- If
.reg
is applied on an anonymous value, then extrapolate a name suggestion based on the destination variable. This is part of the destination, so it adds_part
suffix to the name of the destination. In case of several parts, we create an enumeration. E.g.:
val i = DFUInt(8) <> IN
val o = DFUInt(8) <> OUT
val z = DFUInt(8) <> OUT
o := (i + 1).reg //o_part_reg
z := ((i + 1).reg + 7).reg(2) //z_part1_reg, z_part2_reg1, z_part2_reg2
Attributes
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trait Singletontrait Producttrait Mirrorclass Stagetrait HasTypeNametrait Serializabletrait Producttrait Equalsclass Objecttrait Matchableclass AnyShow all
- Self type
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DropRegAliases.type
This stage transforms a register-transfer (RT) design/domain into a valid event-driven (ED) design/domain. For this purpose it does the following: a. Adds clock and reset ports and connects them across designs. a. Converts the design/domain domainType
from RT to ED. a. Adds combinational process blocks and moves the core logic to it. a. Drops register and wire declarations in favor of regular variable declarations. There are two kinds of variable declarations: local and global. Local variable declarations will appear inside the combinational process block and assignments to these variables are always blocking. Global variables are declared outside the process blocks (within the scope of the design/domain) and assignments to them are always non-blocking. a. Adds a sequential process block according to the clock and reset parameters and adds the register next value assignments to it.
This stage transforms a register-transfer (RT) design/domain into a valid event-driven (ED) design/domain. For this purpose it does the following: a. Adds clock and reset ports and connects them across designs. a. Converts the design/domain domainType
from RT to ED. a. Adds combinational process blocks and moves the core logic to it. a. Drops register and wire declarations in favor of regular variable declarations. There are two kinds of variable declarations: local and global. Local variable declarations will appear inside the combinational process block and assignments to these variables are always blocking. Global variables are declared outside the process blocks (within the scope of the design/domain) and assignments to them are always non-blocking. a. Adds a sequential process block according to the clock and reset parameters and adds the register next value assignments to it.
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trait Singletontrait Producttrait Mirrorclass Stagetrait HasTypeNametrait Serializabletrait Producttrait Equalsclass Objecttrait Matchableclass AnyShow all
- Self type
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DropRegsWires.type
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trait Singletontrait Producttrait Mirrorclass Stagetrait HasTypeNametrait Serializabletrait Producttrait Equalsclass Objecttrait Matchableclass AnyShow all
- Self type
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trait Singletontrait Producttrait Mirrorclass Stagetrait HasTypeNametrait Serializabletrait Producttrait Equalsclass Objecttrait Matchableclass AnyShow all
- Self type
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DropUnreferencedVars.type
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trait Singletontrait Producttrait Mirrorclass Stagetrait HasTypeNametrait Serializabletrait Producttrait Equalsclass Objecttrait Matchableclass AnyShow all
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ExplicitClkRstCfg.type
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trait Singletontrait Producttrait Mirrorclass Stagetrait HasTypeNametrait Serializabletrait Producttrait Equalsclass Objecttrait Matchableclass AnyShow all
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ExplicitNamedVars.type
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trait Singletontrait Producttrait Mirrorclass Stagetrait HasTypeNametrait Serializabletrait Producttrait Equalsclass Objecttrait Matchableclass AnyShow all
- Self type
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ExplicitPrev.type
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class Objecttrait Matchableclass Any
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object given_HasDB_DB.type
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class Objecttrait Matchableclass Any
- Self type
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NamedAliases.type
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trait Singletontrait Producttrait Mirrorclass Stagetrait HasTypeNametrait Serializabletrait Producttrait Equalsclass Objecttrait Matchableclass AnyShow all
- Self type
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NamedSelection.type
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class Objecttrait Matchableclass Any
- Self type
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OrderMembers.type
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trait Singletontrait Producttrait Mirrorclass Stagetrait HasTypeNametrait Serializabletrait Producttrait Equalsclass Objecttrait Matchableclass AnyShow all
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PrintCodeString.type
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trait Singletontrait Producttrait Mirrorclass Stagetrait HasTypeNametrait Serializabletrait Producttrait Equalsclass Objecttrait Matchableclass AnyShow all
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SanityCheck.type
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trait Singletontrait Producttrait Mirrorclass Stagetrait HasTypeNametrait Serializabletrait Producttrait Equalsclass Objecttrait Matchableclass AnyShow all
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SimpleOrderMembers.type
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trait HasTypeNametrait Serializabletrait Producttrait Equalsclass Objecttrait Matchableclass AnyShow all
- Known subtypes
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object VerilogBackend.typeobject VHDLBackend.typeobject AddClkRst.typeobject ConnectClkRst.typeobject DropBAssignFromSeqProc.typeobject DropBinds.typeclass DropLocalDclsobject DropCondDcls.typeobject DropLocalDcls.typeobject DropRegAliases.typeobject DropRegsWires.typeobject DropUnreferencedAnons.typeobject DropUnreferencedVars.typeobject ExplicitClkRstCfg.typeobject ExplicitNamedVars.typeobject ExplicitPrev.typeobject PrintCodeString.typeobject SanityCheck.typeobject ToED.typeobject ToRT.typeobject UniqueDesigns.typeobject VHDLProcToVerilog.typeobject ViaConnection.typeShow all
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- object
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trait LogSupporttrait LazyLoggertrait LoggingMethodstrait Serializableclass Objecttrait Matchableclass AnyShow all
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class Objecttrait Matchableclass Any
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StageRunner.type
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- Companion
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class Objecttrait Matchableclass Any
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- Companion
- class
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class Objecttrait Matchableclass Any
- Self type
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StagedDesign.type
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trait Singletontrait Producttrait Mirrorclass Stagetrait HasTypeNametrait Serializabletrait Producttrait Equalsclass Objecttrait Matchableclass AnyShow all
- Self type
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UniqueDesigns.type
This stage transforms a sequential process from a VHDL style to Verilog style. E.g.,
This stage transforms a sequential process from a VHDL style to Verilog style. E.g.,
process(clk):
if (clk.rising)
....
is transformed into
process(clk.rising):
....
Attributes
- Supertypes
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trait Singletontrait Producttrait Mirrorclass Stagetrait HasTypeNametrait Serializabletrait Producttrait Equalsclass Objecttrait Matchableclass AnyShow all
- Self type
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VHDLProcToVerilog.type
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trait Singletontrait Producttrait Mirrorclass Stagetrait HasTypeNametrait Serializabletrait Producttrait Equalsclass Objecttrait Matchableclass AnyShow all
- Self type
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ViaConnection.type