dfhdl-compiler-stages
API
Generated with
dfhdl-compiler-stages/dfhdl/dfhdl.compiler/dfhdl.compiler.stages/dfhdl.compiler.stages.verilog/VerilogPrinter

VerilogPrinter

dfhdl.compiler.stages.verilog.VerilogPrinter
class VerilogPrinter(using val getSet: MemberGetSet, val printerOptions: PrinterOptions) extends Printer

Attributes

Graph
Supertypes
trait Printer
trait AbstractOwnerPrinter
trait AbstractValPrinter
trait AbstractTokenPrinter
trait AbstractTypePrinter
class Object
trait Matchable
class Any
Show all

Members list

Type members

Types

Value members

Concrete methods

def alignCode(cs: String): String
def colorCode(cs: String): String
def csAnnotations(meta: Meta): String
def csAssignment(lhsStr: String, rhsStr: String): String
def csCommentEOL(comment: String): String
def csCommentInline(comment: String): String
def csConnection(lhsStr: String, rhsStr: String, directionStr: String): String
def csDocString(doc: String): String
override def csGlobalFileContent: String

Attributes

Definition Classes
Printer
def csLazyConnection(lhsStr: String, rhsStr: String, directionStr: String): String
def csNBAssignment(lhsStr: String, rhsStr: String): String
def csOpenKeyWord: String
def csTimer(timer: Timer): String
def csViaConnection(lhsStr: String, rhsStr: String, directionStr: String): String
def csViaConnectionSep: String
def designFileName(designName: String): String
def globalFileName: String
def unsupported: Nothing

Inherited methods

def csBlockBegin: String

Attributes

Inherited from:
VerilogOwnerPrinter (hidden)
def csBlockEnd: String

Attributes

Inherited from:
VerilogOwnerPrinter (hidden)
def csClkCfg(clkCfg: ClkCfg): String

Attributes

Inherited from:
Printer
def csClkEdgeCfg(edgeCfg: EdgeCfg): String

Attributes

Inherited from:
Printer
def csConditionalExprRel(csExp: String, ch: Header): String

Attributes

Inherited from:
VerilogValPrinter (hidden)
final def csDB: String

Attributes

Inherited from:
Printer
def csDFBitBubbleChar: Char

Attributes

Inherited from:
VerilogTokenPrinter (hidden)
def csDFBitFormat(bitRep: String): String

Attributes

Inherited from:
VerilogTokenPrinter (hidden)
def csDFBits(dfType: DFBits, typeCS: Boolean): String

Attributes

Inherited from:
VerilogTypePrinter (hidden)
def csDFBitsBinFormat(binRep: String): String

Attributes

Inherited from:
VerilogTokenPrinter (hidden)
final def csDFBitsData(dfType: DFBits, data: (BitVector, BitVector)): String

Attributes

Inherited from:
AbstractTokenPrinter
def csDFBitsHexFormat(hexRep: String, width: Int): String

Attributes

Inherited from:
VerilogTokenPrinter (hidden)
def csDFBitsHexFormat(hexRep: String): String

Attributes

Inherited from:
VerilogTokenPrinter (hidden)
def csDFBoolFormat(value: Boolean): String

Attributes

Inherited from:
VerilogTokenPrinter (hidden)
def csDFBoolOrBit(dfType: DFBoolOrBit, typeCS: Boolean): String

Attributes

Inherited from:
VerilogTypePrinter (hidden)
final def csDFBoolOrBitData(dfType: DFBoolOrBit, data: Option[Boolean]): String

Attributes

Inherited from:
AbstractTokenPrinter
def csDFCaseBlockEmpty: String

Attributes

Inherited from:
VerilogOwnerPrinter (hidden)
def csDFCaseGuard(guardRef: GuardRef): String

Attributes

Inherited from:
VerilogOwnerPrinter (hidden)
def csDFCaseKeyword: String

Attributes

Inherited from:
VerilogOwnerPrinter (hidden)
def csDFCasePattern(pattern: Pattern): String

Attributes

Inherited from:
AbstractOwnerPrinter
def csDFCasePatternAlternativeToken: String

Attributes

Inherited from:
VerilogOwnerPrinter (hidden)
def csDFCasePatternBind(pattern: Bind): String

Attributes

Inherited from:
VerilogOwnerPrinter (hidden)
def csDFCasePatternBindSI(pattern: BindSI): String

Attributes

Inherited from:
VerilogOwnerPrinter (hidden)
def csDFCasePatternCatchAll: String

Attributes

Inherited from:
VerilogOwnerPrinter (hidden)
def csDFCasePatternStruct(pattern: Struct): String

Attributes

Inherited from:
VerilogOwnerPrinter (hidden)
def csDFCaseSeparator: String

Attributes

Inherited from:
VerilogOwnerPrinter (hidden)
final def csDFCaseStatement(caseBlock: DFCaseBlock): String

Attributes

Inherited from:
AbstractOwnerPrinter
final def csDFConditional(ch: Header): String

Attributes

Inherited from:
AbstractOwnerPrinter
final def csDFConditionalBlock(cb: Block): String

Attributes

Inherited from:
AbstractOwnerPrinter
def csDFDecimal(dfType: DFDecimal, typeCS: Boolean): String

Attributes

Inherited from:
VerilogTypePrinter (hidden)
final def csDFDecimalData(dfType: DFDecimal, data: Option[BigInt]): String

Attributes

Inherited from:
AbstractTokenPrinter
def csDFDesignBlockDcl(design: DFDesignBlock): String

Attributes

Inherited from:
VerilogOwnerPrinter (hidden)
def csDFDesignBlockInst(design: DFDesignBlock): String

Attributes

Inherited from:
VerilogOwnerPrinter (hidden)
def csDFElseIfStatement(csCond: String): String

Attributes

Inherited from:
VerilogOwnerPrinter (hidden)
def csDFElseStatement: String

Attributes

Inherited from:
VerilogOwnerPrinter (hidden)
def csDFEnum(dfType: DFEnum, typeCS: Boolean): String

Attributes

Inherited from:
VerilogTypePrinter (hidden)
def csDFEnumData(dfType: DFEnum, data: Option[BigInt]): String

Attributes

Inherited from:
VerilogTokenPrinter (hidden)
def csDFEnumDcl(dfType: DFEnum, global: Boolean): String

Attributes

Inherited from:
VerilogTypePrinter (hidden)
final def csDFIfElseStatement(ifBlock: DFIfElseBlock): String

Attributes

Inherited from:
AbstractOwnerPrinter
def csDFIfEnd: String

Attributes

Inherited from:
VerilogOwnerPrinter (hidden)
def csDFIfStatement(csCond: String): String

Attributes

Inherited from:
VerilogOwnerPrinter (hidden)
def csDFMatchEnd: String

Attributes

Inherited from:
VerilogOwnerPrinter (hidden)
def csDFMatchStatement(csSelector: String): String

Attributes

Inherited from:
VerilogOwnerPrinter (hidden)
final def csDFMember(member: DFMember): String

Attributes

Inherited from:
Printer
final def csDFMembers(members: List[DFMember]): String

Attributes

Inherited from:
AbstractOwnerPrinter
final def csDFNet(net: DFNet): String

Attributes

Inherited from:
Printer
def csDFOpaque(dfType: DFOpaque, typeCS: Boolean): String

Attributes

Inherited from:
VerilogTypePrinter (hidden)
def csDFOpaqueData(dfType: DFOpaque, data: Any): String

Attributes

Inherited from:
VerilogTokenPrinter (hidden)
def csDFOpaqueDcl(dfType: DFOpaque): String

Attributes

Inherited from:
VerilogTypePrinter (hidden)
final def csDFOwnerBody(owner: DFOwner): String

Attributes

Inherited from:
AbstractOwnerPrinter
final def csDFOwnerLateBody(owner: DFOwner): String

Attributes

Inherited from:
AbstractOwnerPrinter
def csDFSIntFormatBig(value: BigInt, width: Int): String

Attributes

Inherited from:
VerilogTokenPrinter (hidden)
def csDFSIntFormatSmall(value: BigInt, width: Int): String

Attributes

Inherited from:
VerilogTokenPrinter (hidden)
def csDFSIntTokenFromBits(csBits: String): String

Attributes

Inherited from:
VerilogTokenPrinter (hidden)
def csDFStruct(dfType: DFStruct, typeCS: Boolean): String

Attributes

Inherited from:
VerilogTypePrinter (hidden)
def csDFStructData(dfType: DFStruct, data: List[Any]): String

Attributes

Inherited from:
VerilogTokenPrinter (hidden)
def csDFStructDcl(dfType: DFStruct): String

Attributes

Inherited from:
VerilogTypePrinter (hidden)
final def csDFToken(token: DFTokenAny): String

Attributes

Inherited from:
AbstractTokenPrinter
final def csDFTokenSeq(tokenSeq: Seq[DFTokenAny]): String

Attributes

Inherited from:
AbstractTokenPrinter
def csDFTuple(fieldList: List[DFType], typeCS: Boolean): String

Attributes

Inherited from:
VerilogTypePrinter (hidden)
def csDFTupleData(dfTypes: List[DFType], data: List[Any]): String

Attributes

Inherited from:
VerilogTokenPrinter (hidden)
final def csDFType(dfType: DFType, typeCS: Boolean): String

Attributes

Inherited from:
AbstractTypePrinter
def csDFUIntFormatBig(value: BigInt, width: Int): String

Attributes

Inherited from:
VerilogTokenPrinter (hidden)
def csDFUIntFormatSmall(value: BigInt, width: Int): String

Attributes

Inherited from:
VerilogTokenPrinter (hidden)
def csDFUIntTokenFromBits(csBits: String): String

Attributes

Inherited from:
VerilogTokenPrinter (hidden)
def csDFValAliasApplyIdx(dfVal: ApplyIdx): String

Attributes

Inherited from:
VerilogValPrinter (hidden)
def csDFValAliasApplyRange(dfVal: ApplyRange): String

Attributes

Inherited from:
VerilogValPrinter (hidden)
def csDFValAliasAsIs(dfVal: AsIs): String

Attributes

Inherited from:
VerilogValPrinter (hidden)
final def csDFValAliasExpr(dfVal: Alias): String

Attributes

Inherited from:
AbstractValPrinter
def csDFValAliasHistory(dfVal: History): String

Attributes

Inherited from:
VerilogValPrinter (hidden)
def csDFValAliasRegDIN(dfVal: RegDIN): String

Attributes

Inherited from:
VerilogValPrinter (hidden)
def csDFValAliasSelectField(dfVal: SelectField): String

Attributes

Inherited from:
VerilogValPrinter (hidden)
def csDFValConstDcl(dfVal: Const): String

Attributes

Inherited from:
VerilogValPrinter (hidden)
final def csDFValConstExpr(dfVal: Const): String

Attributes

Inherited from:
AbstractValPrinter
def csDFValDcl(dfVal: Dcl): String

Attributes

Inherited from:
VerilogValPrinter (hidden)
final def csDFValExpr(dfValExpr: CanBeExpr): String

Attributes

Inherited from:
AbstractValPrinter
def csDFValFuncExpr(dfVal: Func): String

Attributes

Inherited from:
VerilogValPrinter (hidden)
def csDFValNamed(dfVal: DFVal): String

Attributes

Inherited from:
VerilogValPrinter (hidden)
final def csDFValRef(dfVal: DFVal, fromOwner: DFOwner): String

Attributes

Inherited from:
AbstractValPrinter
def csDFVector(dfType: DFVector, typeCS: Boolean): String

Attributes

Inherited from:
VerilogTypePrinter (hidden)
def csDFVectorData(dfType: DFVector, data: Vector[Any]): String

Attributes

Inherited from:
VerilogTokenPrinter (hidden)
def csDFVectorRanges(dfType: DFType): String

Attributes

Inherited from:
VerilogTypePrinter (hidden)
final def csDocString(meta: Meta): String

Attributes

Inherited from:
Printer
def csDomainBlock(pb: DomainBlock): String

Attributes

Inherited from:
VerilogOwnerPrinter (hidden)
final def csFile(design: DFDesignBlock): String

Attributes

Inherited from:
Printer
def csFreqUnit(freq: Freq): String

Attributes

Inherited from:
Printer
final def csGlobalTypeDcls: String

Attributes

Inherited from:
AbstractTypePrinter
def csIfBlockEmpty: String

Attributes

Inherited from:
VerilogOwnerPrinter (hidden)
def csLibrary(inSimulation: Boolean): String

Attributes

Inherited from:
VerilogOwnerPrinter (hidden)
final def csLocalTypeDcls(design: DFDesignBlock): String

Attributes

Inherited from:
AbstractTypePrinter
def csModuleDcl(design: DFDesignBlock): String

Attributes

Inherited from:
VerilogOwnerPrinter (hidden)
def csNameCfg(nameCfg: NameCfg): String

Attributes

Inherited from:
Printer
final def csNamedDFTypeDcl(dfType: NamedDFType, global: Boolean): String

Attributes

Inherited from:
AbstractTypePrinter
final def csOpenPorts(owner: DFOwner): List[String]

Attributes

Inherited from:
Printer
def csProcessBlock(pb: ProcessBlock): String

Attributes

Inherited from:
VerilogOwnerPrinter (hidden)
def csRTDomainCfg(cfg: RTDomainCfg): String

Attributes

Inherited from:
Printer
def csRTDomainCfg(clkCfg: ClkCfg, rstCfg: RstCfg): String

Attributes

Inherited from:
Printer
def csRatioUnit(ratio: Ratio): String

Attributes

Inherited from:
Printer
final def csRef(ref: TwoWayAny): String

Attributes

Inherited from:
AbstractValPrinter
final def csRelVal(alias: Alias): String

Attributes

Inherited from:
AbstractValPrinter
def csRstActiveCfg(activeCfg: ActiveCfg): String

Attributes

Inherited from:
Printer
def csRstCfg(rstCfg: RstCfg): String

Attributes

Inherited from:
Printer
def csRstModeCfg(modeCfg: ModeCfg): String

Attributes

Inherited from:
Printer
final def csSimpleRef(ref: TwoWayAny): String

Attributes

Inherited from:
AbstractValPrinter
def csTimeUnit(time: Time): String

Attributes

Inherited from:
Printer
def csTimerIsActive(dfVal: IsActive): String

Attributes

Inherited from:
VerilogValPrinter (hidden)
def defsName: String

Attributes

Inherited from:
VerilogOwnerPrinter (hidden)
def fileSuffix: String

Attributes

Inherited from:
VerilogOwnerPrinter (hidden)
final def formatCode(cs: String): String

Attributes

Inherited from:
Printer
def moduleName(design: DFDesignBlock): String

Attributes

Inherited from:
VerilogOwnerPrinter (hidden)
final def printedDB: DB

Attributes

Inherited from:
Printer

Concrete fields

final val normalizeConnection: Boolean
final val normalizeViaConnection: Boolean
val verilogKW: Set[String]
val verilogOps: Set[String]
val verilogTypes: Set[String]

Inherited fields

val TUPLE_MIN_INDEXING: Int

Attributes

Inherited from:
VerilogValPrinter (hidden)
val alignEnable: Align

Attributes

Inherited from:
Printer
val allowBitsBinModeInHex: Boolean

Attributes

Inherited from:
VerilogTokenPrinter (hidden)
val allowBitsExplicitWidth: Boolean

Attributes

Inherited from:
VerilogTokenPrinter (hidden)
val allowDecimalBigInt: Boolean

Attributes

Inherited from:
VerilogTokenPrinter (hidden)
val colorEnable: Color

Attributes

Inherited from:
Printer
val keyword2Color: String

Attributes

Inherited from:
Printer
val keywordColor: String

Attributes

Inherited from:
Printer
val maxTokensPerLine: Int

Attributes

Inherited from:
VerilogTokenPrinter (hidden)
val supportLogicType: Boolean

Attributes

Inherited from:
VerilogValPrinter (hidden)
val typeColor: String

Attributes

Inherited from:
Printer
val useStdSimLibrary: Boolean

Attributes

Inherited from:
VerilogOwnerPrinter (hidden)

Givens

Givens

given getSet: MemberGetSet
given printer: TPrinter
given printerOptions: PrinterOptions
Generated with