abstract class OrderedDecoupledHWIOTester extends HWIOTester
Base class supports implementation of test circuits of modules that use Decoupled inputs and either Decoupled or Valid outputs Multiple decoupled inputs are supported. Testers that subclass this will be strictly ordered. Input will flow into their devices asynchronously but in order they were generated be compared in the order they are generated
- Annotations
- @deprecated
- Deprecated
(Since version chisel-iotesters 2.5.0) chisel-iotesters is end-of-life. Use chiseltest instead, see https://www.chisel-lang.org/chiseltest/migrating-from-iotesters.
- Source
- OrderedDecoupledHWIOTester.scala
class XTimesXTester extends [[OrderedDecoupledHWIOTester]] { val device_under_test = new XTimesY test_block { for { i <- 0 to 10 j <- 0 to 10 } { input_event(device_under_test.io.in.x -> i, device_under_test.in.y -> j) output_event(device_under_test.io.out.z -> i*j) } } }
an input event is a series of values that will be gated into the decoupled input interface at the same time an output event is a series of values that will be tested at the same time independent small state machines are set up for input and output interface all inputs regardless of interfaces are submitted to the device under test in the order in which they were created likewise, all outputs regardless of which interface are tested in the same order that they were created
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- new OrderedDecoupledHWIOTester()
Type Members
- class GlobalEventCounter extends AnyRef
- case class TestingEvent(port_values: Map[Data, BigInt], event_number: Int) extends Product with Serializable
Abstract Value Members
- abstract val device_under_test: Module
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- HWIOTester
Concrete Value Members
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- final def ##: Int
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- def IO[T <: Data](iodef: T): T
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- def _bindIoInPlace(iodef: Data): Unit
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- def _compatAutoWrapPorts(): Unit
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- def checkAndGetCommonDecoupledOrValidParentPort(pokes: Seq[(Data, BigInt)], must_be_decoupled: Boolean = true, event_number: Int): Either[DecoupledIO[Data], ValidIO[Data]]
Validate that all pokes ports are members of the same DecoupledIO makes a list of all decoupled parents based on the ports referenced in pokes
- def circuitName: String
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- final val clock: Clock
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- @throws(classOf[java.lang.CloneNotSupportedException]) @native() @HotSpotIntrinsicCandidate()
- val compileOptions: CompileOptions
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- val control_port_to_input_values: HashMap[DecoupledIO[Data], ArrayBuffer[TestingEvent]]
- val decoupled_control_port_to_output_values: HashMap[DecoupledIO[Data], ArrayBuffer[TestingEvent]]
- def desiredName: String
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- var enable_all_debug: Boolean
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- var enable_printf_debug: Boolean
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- HWIOTester
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- def finish(): Unit
this builds a circuit to load inputs and circuits to test outputs that are controlled by either a decoupled or valid
this builds a circuit to load inputs and circuits to test outputs that are controlled by either a decoupled or valid
- Definition Classes
- OrderedDecoupledHWIOTester → HWIOTester → BasicTester
- final def getClass(): Class[_ <: AnyRef]
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- def getCommands: Seq[Command]
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- def getCommonValidParentPort(expects: Seq[(Data, BigInt)], event_number: Int): Either[DecoupledIO[Data], ValidIO[Data]]
Validate that all pokes ports are members of the same DecoupledIO or ValidIO makes a list of all decoupled parents based on the ports referenced in pokes
- def getModulePorts: Seq[Data]
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- protected[chisel3]
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- BaseModule
- def hasSeed: Boolean
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- def hashCode(): Int
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- def inputEvent(pokes: (Data, BigInt)*): Unit
- val input_event_list: ArrayBuffer[Seq[(Data, BigInt)]]
- def instanceName: String
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- val io: Bundle
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- var io_info: IOAccessor
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- final def isInstanceOf[T0]: Boolean
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- def logPrintfDebug(fmt: String, args: Bits*): Unit
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- final lazy val name: String
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- def nameIds(rootClass: Class[_]): HashMap[HasId, String]
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- def outputEvent(expects: (Data, BigInt)*): Unit
- val output_event_list: ArrayBuffer[Seq[(Data, BigInt)]]
- def parentModName: String
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- def parentPathName: String
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- HasId → InstanceId
- def pathName: String
- Definition Classes
- HasId → InstanceId
- def popCount(n: Long): Int
- Definition Classes
- BasicTester
- val port_to_decoupled: HashMap[Data, DecoupledIO[Data]]
- val port_to_valid: HashMap[Data, ValidIO[Data]]
- def portsContains(elem: Data): Boolean
- Attributes
- protected
- Definition Classes
- BaseModule
- def portsSize: Int
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- protected
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- BaseModule
- def processInputEvents(): Unit
iterate over recorded events, checking constraints on ports referenced, etc.
iterate over recorded events, checking constraints on ports referenced, etc. use poke and expect to record
- def processOutputEvents(): Unit
- final val reset: Reset
- Definition Classes
- Module
- val rnd: Random.type
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- HWIOTester
- def stop()(implicit sourceInfo: SourceInfo): Unit
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- BasicTester
- def suggestName(seed: => String): OrderedDecoupledHWIOTester.this.type
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- final def toTarget: ModuleTarget
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- val valid_control_port_to_output_values: HashMap[ValidIO[Data], ArrayBuffer[TestingEvent]]
- final def wait(arg0: Long, arg1: Int): Unit
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- @throws(classOf[java.lang.InterruptedException])
- final def wait(arg0: Long): Unit
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- final def wait(): Unit
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Deprecated Value Members
- def finalize(): Unit
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- lazy val getPorts: Seq[Port]
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- @deprecated
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(Since version Chisel 3.5) Use DataMirror.modulePorts instead. this API will be removed in Chisel 3.6
- def override_clock: Option[Clock]
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(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_clock_=(rhs: Option[Clock]): Unit
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- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset: Option[Bool]
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- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset_=(rhs: Option[Bool]): Unit
- Attributes
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- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation