EdgeData
graph
EdgeNotFoundException
graph
EliminateTargetPaths
transforms
EmitAllModulesAnnotation
firrtl
EmitAnnotation
firrtl
EmitCircuitAnnotation
firrtl
EmittedAnnotation
firrtl
EmittedCircuit
firrtl
EmittedCircuitAnnotation
firrtl
EmittedComponent
firrtl
EmittedFirrtlCircuit
firrtl
EmittedFirrtlCircuitAnnotation
firrtl
EmittedFirrtlModule
firrtl
EmittedFirrtlModuleAnnotation
firrtl
EmittedModule
firrtl
EmittedModuleAnnotation
firrtl
EmittedVerilogCircuit
firrtl
EmittedVerilogCircuitAnnotation
firrtl
EmittedVerilogModule
firrtl
EmittedVerilogModuleAnnotation
firrtl
Emitter
firrtl
EmitterException
firrtl
EmptyExpression
firrtl
EmptyStmt
ir
EnNotUInt
CheckTypes
EnableNotUInt
CheckTypes
Eq
PrimOps
Error
LogLevel
Errors
passes
EulerTour
graph
ExceptOnError
options
ExecutionOptionsManager
firrtl
ExitCode
options
ExitFailure
options
ExitSuccess
options
ExpKind
firrtl
ExpWidth
firrtl
ExpandConnects
passes
ExpandWhens
passes
ExprForeach
Foreachers
ExprMap
Mappers
Expression
ir
ExpressionSerializer
JsonProtocol
ExtModule
ir
ExtModulePathAnnotation
transforms
e1
WrappedExpression
edgeData
EdgeData
edgeDataMap
EdgeData
MutableEdgeData
emit
Emitter
FirrtlEmitter
VerilogEmitter
emitOneFilePerModule
FirrtlExecutionOptions
emitType
FirrtlExecutionSuccess
emitVerilogBind
VerilogRender
emit_streams
VerilogRender
emit_verilog
VerilogRender
emitted
FirrtlExecutionSuccess
emittedCircuitOption
CircuitState
emittedComponents
CircuitState
emitter
Compiler
EmitAllModulesAnnotation
EmitAnnotation
EmitCircuitAnnotation
HighFirrtlCompiler
LowFirrtlCompiler
MiddleFirrtlCompiler
MinimumVerilogCompiler
NoneCompiler
SystemVerilogCompiler
VerilogCompiler
en
Print
Stop
encapsulatingModule
IsComponent
equals
MemoizedHash
WrappedExpression
WrappedType
WrappedWidth
IntWidth
eqw
WrappedWidth
error
Utils
Logger
errorNotFound
DontTouchAnnotation
errorOnChirrtl
CheckChirrtl
CheckHighForm
CheckHighFormLike
errors
Errors
escape
StringLit
exceptions
PassExceptions
execute
AddDescriptionNodes
Driver
FirrtlEmitter
SeqTransform
Transform
VerilogEmitter
GetNamespace
EliminateTargetPaths
CheckResets
Stage
DeadCodeElimination
InferWidths
InlineInstances
LowerTypes
Pass
RemoveCHIRRTL
Uniquify
ZeroWidth
ClockListTransform
CreateMemoryAnnotations
InferReadWrite
ReplSeqMem
ReplaceMemMacros
ResolveMemoryReference
SimpleTransform
WiringTransform
BlackBoxSourceHelper
CheckCombLoops
CombineCats
ConstantPropagation
DeadCodeElimination
DedupModules
FixAddingNegativeLiterals
Flatten
FlattenRegUpdate
GroupAndDedup
GroupComponents
IdentityTransform
InferResets
InlineBitExtractionsTransform
InlineCastsTransform
InlineNotsTransform
LegalizeAndReductionsTransform
LegalizeClocksTransform
RemoveKeywordCollisions
RemoveReset
RemoveWires
RenameModules
ReplaceTruncatingArithmetic
SimplifyMems
TopWiringTransform
AnalyzeCircuit
AnalyzeCircuit
executeEmptyMemStmt
ZeroWidth
executeExpectingFailure
BackendCompilationUtilities
executeExpectingSuccess
BackendCompilationUtilities
executeModule
AddDescriptionNodes
existingModules
DuplicationHelper
exitOnHelp
HasParser
exp
WGeq
FIRRTLParser
DataRef
WidthGeqConstraintAnnotation
expToString
VerilogMemDelays
expandCatArgs
CombineCats
expandHierarchy
DuplicationHelper
expandPrefixes
Utils
expandRef
Utils
expandWhens
ExpandWhens
expr
WSubAccess
WSubField
WSubIndex
ComponentName
Connect
IsInvalid
PartialConnect
SubAccess
SubField
SubIndex
exprs
Attach
exps
CDefMPort
extractRefs
DeadCodeElimination