IRToWorkingIR
firrtl
IdentityTransform
transforms
IgnoreInfo
Parser
IllegalAnalogDeclaration
CheckTypes
IllegalAttachExp
CheckTypes
IllegalChirrtlMemException
CheckHighForm
IllegalMemLatencyException
CheckHighFormLike
IllegalRenameException
RenameMap
IllegalResetType
CheckTypes
IllegalUnknownType
CheckTypes
IncorrectNumArgsException
CheckHighFormLike
IncorrectNumConstsException
CheckHighFormLike
Index
TargetToken fromIntToTargetToken
IndexNotUInt
CheckTypes
IndexOnNonVector
CheckTypes
IndexTooLarge
CheckTypes
InferReadWrite
memlib
InferReadWriteAnnotation
memlib
InferReadWritePass
memlib
InferResets
transforms
InferResetsException
InferResets
InferTypes
passes
InferWidths
passes
Info
ir LogLevel
InfoMap
ExpandWhens
InfoMode
Parser
InfoModeAnnotation
stage
InfoSerializer
JsonProtocol
Init
TargetToken
InlineAnnotation
passes
InlineBitExtractionsTransform
transforms
InlineCastsTransform
transforms
InlineInstances
passes
InlineNotsTransform
transforms
Input
ir
InputAnnotationFileAnnotation
options
InputConfigFileName
memlib
InstPath
TopWiringTransform
Instance
TargetToken fromDefInstanceToTargetToken fromStringToTargetToken fromWDefInstanceToTargetToken
InstanceGraph
analyses
InstanceKind
firrtl
InstanceLoop
CheckHighFormLike
InstanceOfModuleMap
DuplicationHelper
InstanceTarget
annotations
InstanceTargetSerializer
JsonProtocol
IntParam
ir
IntWidth
ir
InvalidAccessException
CheckHighFormLike
InvalidAnnotationFileException
annotations
InvalidAnnotationJSONException
annotations
InvalidConnect
CheckTypes
InvalidEscapeCharException
firrtl
InvalidLOCException
CheckHighFormLike
InvalidRegInit
CheckTypes
InvalidStringLitException
firrtl
IsComponent
annotations
IsDeclaration
ir
IsInvalid
ir
IsMember
annotations
IsMemberSerializer
JsonProtocol
IsModule
annotations
IsModuleSerializer
JsonProtocol
id
FIRRTLParser
indent
Utils
index
WSubAccess ReferenceTarget SubAccess
inferRW
FirrtlExecutionOptions
inferReadWrite
InferReadWritePass
inferReadWriteStmt
InferReadWritePass
infer_mdir
CInferMDir
infer_mdir_e
CInferMDir
infer_mdir_s
CInferMDir
info
CDefMPort CDefMemory WDefInstance WDefInstanceConnector FIRRTLParser Attach Circuit Conditionally Connect DefInstance DefMemory DefModule DefNode DefRegister DefWire ExtModule FileInfo HasInfo IsInvalid Module PartialConnect Port Print Stop DefAnnotatedMemory Logger
infoMode
FirrtlExecutionOptions
infoModeName
FirrtlExecutionOptions FirrtlOptions
infos
MultiInfo
init
ReferenceTarget DefRegister
initialize
VerilogRender
initialize_mem
VerilogRender
initials
VerilogRender
inline
Utils
inlineTransform
Flatten
inputFileName
ReplSeqMemAnnotation
inputFileNameOverride
FirrtlExecutionOptions
inputForm
AddDescriptionNodes ChirrtlToHighFirrtl Compiler FirrtlEmitter HighFirrtlToMiddleFirrtl IRToWorkingIR LowFirrtlOptimization MiddleFirrtlToLowFirrtl MinimumLowFirrtlOptimization ResolveAndCheck Transform VerilogEmitter GetNamespace EliminateTargetPaths CheckResets DeadCodeElimination InferWidths InlineInstances LowerTypes Pass RemoveCHIRRTL Uniquify ZeroWidth ClockListTransform CreateMemoryAnnotations InferReadWrite ReplSeqMem ReplaceMemMacros ResolveMemoryReference SimpleTransform WiringTransform BlackBoxSourceHelper CheckCombLoops CombineCats ConstantPropagation DeadCodeElimination DedupModules FixAddingNegativeLiterals Flatten FlattenRegUpdate GroupAndDedup GroupComponents IdentityTransform InferResets InlineBitExtractionsTransform InlineCastsTransform InlineNotsTransform LegalizeAndReductionsTransform LegalizeClocksTransform RemoveKeywordCollisions RemoveReset RemoveWires RenameModules ReplaceTruncatingArithmetic SimplifyMems TopWiringTransform AnalyzeCircuit AnalyzeCircuit
inputSuffix
GroupAnnotation
inst
LogicNode
instOf
InstanceTarget IsModule ModuleTarget
instance
InstanceTarget
instdeclares
VerilogRender
intLit
FIRRTLParser
internalTransform
Translator DeletedWrapper Compiler
invalidAssign
VerilogRender
invalidateGraph
DependencyManager
invalidates
DependencyAPI PreservesAll
ir
firrtl
is
TargetToken
isBitExtract
Utils
isCast
Utils
isCircuitTarget
GenericTarget
isClassLoaded
ClassUtils
isCommandAvailable
FileUtils
isComplete
GenericTarget
isComponentTarget
GenericTarget
isLegal
GenericTarget
isLocal
CircuitTarget GenericTarget IsComponent ModuleTarget Target
isModuleTarget
GenericTarget
isOnly
Target
isTemp
Utils
isVCSAvailable
FileUtils