OfModule
TargetToken fromDefInstanceToTargetToken fromDefModuleToTargetToken fromStringToTargetToken fromWDefInstanceToTargetToken
Old
ReadUnderWrite
OneFilePerModule
firrtl
OpNoMixFix
CheckTypes
OpNotAllSameType
CheckTypes
OpNotAllUInt
CheckTypes
OpNotAnalog
CheckTypes
OpNotCorrectType
CheckTypes
OpNotGround
CheckTypes
OpNotUInt
CheckTypes
OptimizableExtModuleAnnotation
transforms
OptionsException
Driver options
OptionsHelpException
options
OptionsView
options
Or
PrimOps
Orientation
ir
Orr
PrimOps
Output
ir
OutputAnnotationFileAnnotation
options
OutputCaptor
Logger
OutputConfig
firrtl
OutputConfigFileName
memlib
OutputFileAnnotation
stage
ofModule
InstanceTarget
ofModuleTarget
InstanceTarget
onExpr
InlineBitExtractionsTransform InlineCastsTransform InlineNotsTransform LegalizeAndReductionsTransform ReplaceTruncatingArithmetic
onMod
CombineCats InlineBitExtractionsTransform InlineCastsTransform InlineNotsTransform LegalizeAndReductionsTransform LegalizeClocksTransform ReplaceTruncatingArithmetic
onModule
AddDescriptionNodes RemoveAllButClocks SimplifyMems
onStmt
AddDescriptionNodes RemoveAllButClocks CombineCats InlineBitExtractionsTransform InlineCastsTransform InlineNotsTransform LegalizeAndReductionsTransform LegalizeClocksTransform RenameModules ReplaceTruncatingArithmetic
one
Utils
op
DoPrim
op_stream
VerilogEmitter
optAdd
GenericTarget
optimize
ConstantPropagation
options
EmitAllModulesAnnotation EmitCircuitAnnotation firrtl HasShellOptions InputAnnotationFileAnnotation OutputAnnotationFileAnnotation TargetDirAnnotation WriteDeletedAnnotation InlineInstances ClockListTransform InferReadWrite MemLibOptions ReplSeqMem CompilerAnnotation FirrtlFileAnnotation FirrtlSourceAnnotation InfoModeAnnotation OutputFileAnnotation RunFirrtlTransformAnnotation CheckCombLoops DeadCodeElimination NoCircuitDedupAnnotation ClassLogLevelAnnotation LogClassNamesAnnotation LogFileAnnotation LogLevelAnnotation
originalMemoryNameOpt
LoadMemoryAnnotation
outputAnnotationFileName
FirrtlExecutionOptions
outputBuffer
ConfWriter YamlFileWriter
outputConfig
ClockListAnnotation ReplSeqMemAnnotation
outputFileName
FirrtlOptions
outputFileNameOverride
FirrtlExecutionOptions
outputForm
AddDescriptionNodes ChirrtlToHighFirrtl Compiler FirrtlEmitter HighFirrtlToMiddleFirrtl IRToWorkingIR LowFirrtlOptimization MiddleFirrtlToLowFirrtl MinimumLowFirrtlOptimization ResolveAndCheck Transform VerilogEmitter GetNamespace EliminateTargetPaths CheckResets DeadCodeElimination InferWidths InlineInstances LowerTypes Pass RemoveCHIRRTL Uniquify ZeroWidth ClockListTransform CreateMemoryAnnotations InferReadWrite ReplSeqMem ReplaceMemMacros ResolveMemoryReference SimpleTransform WiringTransform BlackBoxSourceHelper CheckCombLoops CombineCats ConstantPropagation DeadCodeElimination DedupModules FixAddingNegativeLiterals Flatten FlattenRegUpdate GroupAndDedup GroupComponents IdentityTransform InferResets InlineBitExtractionsTransform InlineCastsTransform InlineNotsTransform LegalizeAndReductionsTransform LegalizeClocksTransform RemoveKeywordCollisions RemoveReset RemoveWires RenameModules ReplaceTruncatingArithmetic SimplifyMems TopWiringTransform AnalyzeCircuit AnalyzeCircuit
outputFunction
TopWiringOutputFilesAnnotation
outputSuffix
ChirrtlForm CircuitForm EmittedComponent EmittedFirrtlCircuit EmittedFirrtlModule EmittedVerilogCircuit EmittedVerilogModule Emitter FirrtlEmitter FirrtlExecutionOptions HighForm LowForm MidForm SystemVerilogEmitter UnknownForm VerilogEmitter GroupAnnotation