UIntLiteral
ir
UIntType
ir
UIntZero
RemoveValidIf
UNKNOWNGENDER
firrtl
UndeclaredReferenceException
CheckHighFormLike
Undefined
ReadUnderWrite
UninferredWidth
CheckWidths
Uniquify
passes
UnknownFlow
firrtl
UnknownForm
firrtl
UnknownKind
firrtl
UnknownType
ir
UnknownWidth
ir
Unserializable
options
UnsupportedBlackboxMemoryException
ReplaceMemMacros
UseInfo
Parser
Utils
firrtl
ug
VerilogMemDelays
unapply
FirrtlExecutionSuccess
Annotation
Target
GroundType
IntWidth
underlying
RenameMap
unescape
StringLit
unique
NodeCount
uniqueFrom
NodeCount
uniquifyField
DedupModules
unreachableModules
InstanceGraph
update
DescriptionAnnotation
VerilogRender
Annotation
LegacyAnnotation
MultiTargetAnnotation
NoTargetAnnotation
SingleTargetAnnotation
ResolvePaths
WidthGeqConstraintAnnotation
CombinationalPath
ExtModulePathAnnotation
GroupAnnotation
updateMemMods
RenameAnnotatedMemoryPorts
ReplaceMemMacros
updateMemStmts
RenameAnnotatedMemoryPorts
ReplaceMemMacros
ResolveMemoryReference
updateStmtRefs
MemTransformUtils
updateStmts
ResolveMaskGranularity
ToMemIR
ut
CheckTypes
RemoveCHIRRTL
util
firrtl