Tail
PrimOps
TailWidthException
CheckWidths
Target
annotations
TargetDirAnnotation
firrtl options
TargetSerializer
JsonProtocol
TargetToken
annotations
TestDirectory
BackendCompilationUtilities
TestOptions
util
ToMemIR
memlib
ToProto
proto
ToWorkingIR
passes
Top
memlib
TopNameAnnotation
DriverCompatibility
TopWiring
transforms
TopWiringAnnotation
TopWiring
TopWiringOutputFilesAnnotation
TopWiring
TopWiringTransform
TopWiring
Trace
LogLevel
Transform
firrtl
TransformClassSerializer
JsonProtocol
TransformLike
options
TransformSerializer
JsonProtocol
Translator
options
Type
ir
TypeForeach
Foreachers
TypeMap
Mappers CInferTypes InferTypes
TypeSerializer
JsonProtocol
t
MemoizedHash WrappedType
tab
VerilogEmitter
target
LegacyAnnotation LoadMemoryAnnotation SingleTargetAnnotation InlineAnnotation ClockListAnnotation NoDedupMemAnnotation SinkAnnotation SourceAnnotation BlackBoxInlineAnno BlackBoxPathAnno BlackBoxResourceAnno DontTouchAnnotation FlattenAnnotation NoDedupAnnotation OptimizableExtModuleAnnotation TopWiringAnnotation
targetDir
OneFilePerModule StageOptions BlackBoxTargetDirAnno
targetDirName
CommonOptions ExecutionOptionsManager
targetFile
SingleFile
targetParent
InstanceTarget IsMember ModuleTarget ReferenceTarget
targetString
LegacyAnnotation
targets
LegacyAnnotation MultiTargetAnnotation ResolvePaths DependencyManager PhaseManager DontTouchAnnotation
terminate
DoNotTerminateOnExit
text
BlackBoxInlineAnno
throwInternalError
Utils
time
Utils
timeStamp
BackendCompilationUtilities
times
Utils
toAnnotationSeq
ShellOption
toAnnotations
CommonOptions FirrtlExecutionOptions
toBitMask
passes
toBits
firrtl
toCircuit
CircuitOption FirrtlFileAnnotation FirrtlSourceAnnotation
toDot
RenderDiGraph
toDotRanked
RenderDiGraph
toDotWithLoops
RenderDiGraph
toExp
AnnotationUtils ToWorkingIR
toGenericTarget
GenericTarget Target
toInfoMode
InfoModeAnnotation
toMem
DefAnnotatedMemory
toNamed
AnnotationUtils CircuitTarget GenericTarget IsComponent ModuleTarget Target
toSIntType
ConvertFixedToSInt
toSeq
AnnotationSeq
toStmt
ToWorkingIR
toStr
CheckFlows CheckGenders
toString
Addw Dshlw Add And Andr AsAsyncReset AsClock AsFixedPoint AsSInt AsUInt BPSet BPShl BPShr Bits Cat Cvt Div Dshl Dshr Eq Geq Gt Head Leq Lt Mul Neg Neq Not Or Orr Pad Rem Shl Shr Sub Tail Xor Xorr Subw WGeq WrappedExpression WrappedWidth FileInfo IntWidth MultiInfo NoInfo MemConf MemPort Lineage Modifications
toSubComponents
AnnotationUtils
toTarget
Utils AnnotationYamlFormat CircuitName CompleteTarget ComponentName GenericTarget ModuleName Named
toTargetTokens
Target
toTokens
fromDefInstanceToTargetToken fromWDefInstanceToTargetToken
toWrappedExpression
Utils
toYaml
AnnotationUtils
to_dir
Utils
to_flip
Utils
to_flow
Utils
to_gender
Utils
tokenize
AnnotationUtils
tokens
CircuitTarget GenericTarget IsComponent ModuleTarget Target
top
Config
topName
CommonOptions ExecutionOptionsManager TopNameAnnotation
topWiringDummyOutputFilesFunction
TopWiringTransform
tour
InstanceGraph
tpe
CDefMPort CDefMemory EmptyExpression VRandom WDefInstance WDefInstanceConnector WInvalid WRef WSubAccess WSubField WSubIndex WVoid DefRegister DefWire DoPrim Expression Field FixedLiteral Mux Port Reference SIntLiteral SubAccess SubField SubIndex UIntLiteral ValidIf VectorType
trace
Logger
transform
Transform LegacyAnnotation DependencyManager Stage TransformLike Translator AddDefaults Checks ConvertLegacyAnnotations GetIncludes WriteOutputAnnotations VerilogMemDelays RunFirrtlTransformAnnotation AddCircuit AddDefaults AddImplicitEmitter AddImplicitOutputFile Checks AddImplicitAnnotationFile AddImplicitEmitter AddImplicitFirrtlFile AddImplicitOutputFile WriteEmitted Checks
transformClass
LegacyAnnotation
transformNodes
DiGraph
transformOrder
DependencyManager
transformOrderToGraphviz
DependencyManager
transformed
MemDelayAndReadwriteTransformer
transforms
ChirrtlToHighFirrtl Compiler HighFirrtlCompiler HighFirrtlToMiddleFirrtl IRToWorkingIR LowFirrtlCompiler LowFirrtlOptimization MiddleFirrtlCompiler MiddleFirrtlToLowFirrtl MinimumLowFirrtlOptimization MinimumVerilogCompiler MinimumVerilogEmitter NoneCompiler ResolveAndCheck SeqTransformBased VerilogCompiler VerilogEmitter annotations InferReadWrite ReplSeqMem firrtl
traversals
firrtl
trigger
Errors
tryName
Namespace
tryToComplete
Target
tutorial
root
tval
Mux
type
FIRRTLParser