RawStringParam
ir
ReadPort
memlib
ReadUnderWrite
ir
ReadWritePort
memlib
Ref
TargetToken
fromStringToTargetToken
RefNotInitializedException
CheckInitialization
Reference
ir
ReferenceTarget
annotations
ReferenceTargetSerializer
JsonProtocol
RegKind
firrtl
RegReqClk
CheckTypes
RegWithFlipException
CheckHighFormLike
RegisteredLibrary
options
RegisteredTransform
options
Rem
PrimOps
RemoveAccesses
passes
RemoveAllButClocks
clocklist
RemoveCHIRRTL
passes
RemoveEmpty
passes
RemoveKeywordCollisions
transforms
RemoveReset
transforms
RemoveValidIf
passes
RemoveWires
transforms
RenameAnnotatedMemoryPorts
memlib
RenameMap
firrtl
RenameModules
transforms
RenameTargetException
RenameMap
RenderDiGraph
graph
ReplSeqMem
memlib
ReplSeqMemAnnotation
memlib
ReplaceAccesses
passes
ReplaceMemMacros
memlib
ReplaceTruncatingArithmetic
transforms
ReqClk
CheckTypes
Reset
TargetToken
ResetExtModuleOutputException
CheckHighFormLike
ResetInputException
CheckHighFormLike
ResetType
ir
ResolveAndCheck
firrtl
ResolveFlows
passes
ResolveGenders
passes
ResolveKinds
passes
ResolveMaskGranularity
memlib
ResolveMemoryReference
memlib
ResolvePaths
transforms
ResolvedAnnotationPaths
firrtl
RunFirrtlTransformAnnotation
stage
rand_string
VerilogRender
rdwrite
DataRef
reachableFrom
DiGraph
reachableModules
InstanceGraph
read
AnnotationYamlFormat
readLatency
DefMemory
DefAnnotatedMemory
readUnderWrite
CDefMemory
DefMemory
DefAnnotatedMemory
readers
DefMemory
MPorts
DefAnnotatedMemory
readwriters
DefMemory
MPorts
DefAnnotatedMemory
realWidth
VRandom
reason
CircularRenameException
IllegalRenameException
record
RenameMap
recordAll
RenameMap
ref
InstanceTarget
IsModule
ModuleTarget
ReferenceTarget
referringModule
Target
regUpdate
VerilogRender
regex
MemConf
registeredLibraries
Shell
registeredTransforms
Shell
remove
GenericTarget
remove_chirrtl_m
RemoveCHIRRTL
remove_chirrtl_s
RemoveCHIRRTL
remove_root
VerilogEmitter
rename
RenameMap
renameExps
LowerTypes
renames
CircuitState
renderNode
RenderDiGraph
replaceExp
InferReadWritePass
VerilogMemDelays
replaceStmt
InferReadWritePass
reportError
ExceptOnError
reset
ReferenceTarget
DefRegister
Logger
reset_block
FIRRTLParser
resolvePaths
CircuitState
resolvePathsOf
CircuitState
resolve_e
ResolveFlows
ResolveGenders
resolve_expr
ResolveKinds
resolve_flow
ResolveFlows
resolve_kinds
ResolveKinds
resolve_s
ResolveFlows
ResolveGenders
resolve_stmt
ResolveKinds
resourceFileName
BlackBoxResourceFileNameAnno
resourceId
BlackBoxResourceAnno
ret
Stop
reverse
DiGraph
rmq
EulerTour
rmqBV
EulerTour
rmqNaive
EulerTour
run
EliminateTargetPaths
Stage
CInferMDir
CInferTypes
CheckFlows
CheckGenders
CheckHighFormLike
CheckInitialization
CheckTypes
CheckWidths
CommonSubexpressionElimination
ConvertFixedToSInt
ExpandConnects
ExpandWhens
InferTypes
InferWidths
InlineInstances
Legalize
PadWidths
Pass
PullMuxes
RemoveAccesses
RemoveEmpty
RemoveValidIf
ReplaceAccesses
ResolveFlows
ResolveGenders
ResolveKinds
SplitExpressions
ToWorkingIR
VerilogModulusCleanup
VerilogPrep
VerilogRename
ZeroLengthVecs
ClockList
RemoveAllButClocks
InferReadWritePass
RenameAnnotatedMemoryPorts
ResolveMaskGranularity
ResolveMemoryReference
ToMemIR
VerilogMemDelays
Wiring
FirrtlStage
DeadCodeElimination
DedupModules
RemoveKeywordCollisions
runTransform
Transform
runTransforms
SeqTransformBased
ruw
FIRRTLParser