OffsetOut

A UGen that writes a signal onto a bus, delaying the signal such that the input will begin to appear on the bus precisely when the encompassing Synth was scheduled according to its OSC bundle. I.e. if the synth is scheduled to be started part way through a control cycle, OffsetOut will maintain the correct offset by buffering the output and delaying it until the exact time that the synth was scheduled for.

This UGen adds ("mixes") the input-signal to the existing contents of the bus.

Multi-channel input signals, for example a PanAz , are written as such to the bus without expansion. That is, the bus index argument is used for the first channel, the second channel will appear on bus + 1 , etc.

If you have an expanding multi-channel input, however, you have to be careful. For example, if you have PanAz.ar(2, SinOsc.ar(Seq(444, 555, 666)) * 0.2, Seq(-1, 0, 1)) , this results in one output UGen carrying one channel, and another one carrying two channels. (The way this works is consistent with SCLang). In order to get the correct behaviour (left outputs of the PanAz summed, and right output of the PanAz summed), wrap this expression in a Mix(...) before passing it to the output UGen.

'''Note''': You cannot currently achieve sample accurate scheduling in SuperCollider. This UGen is therefore more or less useless.

===Examples===

// compare left-right
val sd = SynthDef.recv("offset-out") {
 val x = Impulse.ar(2)
 val y = SubsampleOffset.ir
 y.poll(0, "offset")
 Out      .ar(0, x)
 OffsetOut.ar(1, x)    // right channel will be delayed against left
}

val x = Synth(s)
s ! osc.Bundle.millis(System.currentTimeMillis + 1000, x.newMsg(sd.name, s))